- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10956 > ADAU1961WBCPZ (Analog Devices Inc)IC STEREO AUD CODEC LP 32LFCSP PDF資料下載
參數(shù)資料
| 型號： | ADAU1961WBCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC STEREO AUD CODEC LP 32LFCSP |
| 標準包裝： | 1 |
| 類型： | 音頻編解碼器 |
| 數(shù)據(jù)接口： | I²C，串行，SPI? |
| 分辨率（位）： | 24 b |
| ADC / DAC 數(shù)量： | 2 / 2 |
| 三角積分調(diào)變： | 無 |
| S/N 比，標準 ADC / DAC (db)： | 98 / 98 |
| 動態(tài)范圍，標準 ADC / DAC (db)： | 96 / 98 |
| 電壓 - 電源，模擬： | 2.97 V ~ 3.63 V |
| 電壓 - 電源，數(shù)字： | 2.97 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-EP（5x5） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁
ADAU1961
Data Sheet
Rev. A | Page 30 of 76
AUTOMATIC LEVEL CONTROL (ALC)
The ADAU1961 contains a hardware automatic level control
(ALC). The ALC is designed to continuously adjust the PGA
gain to keep the recording volume constant as the input level
varies.
For optimal noise performance, the ALC uses the analog PGA
to adjust the gain instead of using a digital method. This ensures
that the ADC noise is not amplified at low signal levels.
Extremely small gain step sizes are used to ensure high audio
quality during gain changes.
To use the ALC function, the inputs must be applied either
differentially or pseudo-differentially to input pins LINN and
LINP, for the left channel, and RINN and RINP, for the right
channel. The ALC function is not available for the auxiliary line
input pins, LAUX and RAUX.
A block diagram of the ALC block is shown in Figure 36. The
ALC logic receives the ADC output signals and analyzes these
digital signals to set the PGA gain. The ALC control registers
are used to control the time constants and output levels, as
described in this section.
RIGHT
ADC
LEFT
ADC
MUTE
SERIAL
PORTS
ALC
DIGITAL
ANALOG
INPUT
LEFT
I2C
CONTROL
ANALOG
INPUT
RIGHT
PGA
–12dB TO +35.25dB
0.75dB STEP SIZE
08915-
024
Figure 36. ALC Architecture
ALC PARAMETERS
The ALC function is controlled with the ALC control registers
(Address 0x4011 through Address 0x4014) using the following
parameters:
ALCSEL[2:0]: The ALC select bits are used to enable the
ALC and set the mode to left only, right only, or stereo. In
stereo mode, the greater of the left or right inputs is used
to calculate the gain, and the same gain is then applied to
both the left and right channels.
ALCTARG[3:0]: The ALC target is the desired input
recording level that the ALC attempts to achieve.
ALCATCK[3:0]: The ALC attack time sets how fast the
ALC starts attenuating after a sudden increase in input
level above the ALC target. Although it may seem that
the attack time should be set as fast as possible to avoid
clipping on transients, using a moderate value results in
better overall sound quality. If the value is too fast, the
ALC overreacts to very short transients, causing audible
gain-pumping effects, which sounds worse than using a
moderate value that allows brief periods of clipping on
transients. A typical setting for music recording is 384 ms.
A typical setting for voice recording is 24 ms.
ALCHOLD[3:0]: These bits set the ALC hold time. When
the output signal falls below the target output level, the
gain is not increased unless the output remains below the
target level for the period of time set by the hold time bits.
The hold time is used to prevent the gain from modulating
on a steady low frequency sine wave signal, which would
cause distortion.
ALCDEC[3:0]: The ALC decay time sets how fast the ALC
increases the PGA gain after a sudden decrease in input level
below the ALC target. A very slow setting can be used if the
main function of the ALC is to set a music recording level.
A faster setting can be used if the function of the ALC is to
compress the dynamic range of a voice recording. Using a
very fast decay time can cause audible artifacts such as noise
pumping or distortion. A typical setting for music recording
is 24.58 sec. A typical setting for voice recording is 1.54 sec.
ALCMAX[2:0]: The maximum ALC gain bits are used to
limit the maximum gain that can be programmed into the
ALC. This can be used to prevent excessive noise in the
recording for small input signals. Note that setting this
register to a low value may prevent the ALC from reaching
its target output level, but this behavior is often desirable to
achieve the best overall sound.
Figure 37 shows the dynamic behavior of the PGA gain for a
tone-burst input. The target output is achieved for three differ-
ent input levels, with the effect of attack, hold, and decay shown
in the figure. Note that for very small signals, the maximum PGA
gain may prevent the ALC from achieving its target level; in the
same way, for very large inputs, the minimum PGA gain may
prevent the ALC from achieving its target level (assuming that
the target output level is set to a very low value). The effects of
the PGA gain limit are shown in the input/output graph of
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC908GZ60MFJE | IC MCU 8BIT 60K FLASH 32-LQFP |
| MC908GZ32VFJE | IC MCU 8BIT 32K FLASH 32-LQFP |
| AD74111YRUZ | IC CODEC AUDIO MONO LP 16TSSOP |
| VI-22R-IY-F3 | CONVERTER MOD DC/DC 7.5V 50W |
| CS4270-CZZ | IC CODEC 24BIT 105DB 24TSSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADAU1961WBCPZ-R7 | 功能描述:IC STEREO AUD CODEC LP 32LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標準包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標準 ADC / DAC (db):81.5 / 88 動態(tài)范圍，標準 ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
| ADAU1961WBCPZ-RL | 功能描述:IC STEREO AUD CODEC LP 32LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標準包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標準 ADC / DAC (db):81.5 / 88 動態(tài)范圍，標準 ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
| ADAU1962AWBSTZ | 制造商:Analog Devices 功能描述:AUTOMOTIVE HIGH PERFORMANCE 12 DAC - Trays 制造商:Analog Devices 功能描述:IC DAC 80LQFP 制造商:Analog Devices 功能描述:DAC 24 BITS 48KHZ SPI LQFP 制造商:Analog Devices 功能描述:DAC, 24BIT, 192KSPS, LQFP-80, Resolution (Bits):24bit, Sampling Rate:192kSPS, Input Channel Type:Differential, Single Ended, Supply Voltage Range:3.14V to 3.46V, Digital IC Case Style:LQFP, No. of Pins:80, Data Interface:I2C, SPI |
| ADAU1962AWBSTZ-RL | 功能描述:24 Bit Digital to Analog Converter 12 80-LQFP (14x14) 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):有效 位數(shù):24 數(shù)模轉(zhuǎn)換器數(shù):12 建立時間:- 輸出類型:Voltage - Unbuffered 差分輸出:是 數(shù)據(jù)接口:I2C， SPI 參考類型:內(nèi)部 電壓 - 電源，模擬:3.14 V ~ 3.46 V 電壓 - 電源，數(shù)字:2.25 V ~ 3.46 V INL/DNL（LSB）:- 架構(gòu):三角積分 工作溫度:-40°C ~ 125°C 封裝/外殼:80-LQFP 供應(yīng)商器件封裝:80-LQFP（14x14） 標準包裝:1,000 |
| ADAU1962WBSTZ | 功能描述:24 Bit Digital to Analog Converter 12 80-LQFP (14x14) 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):有效 位數(shù):24 數(shù)模轉(zhuǎn)換器數(shù):12 建立時間:- 輸出類型:Voltage - Unbuffered 差分輸出:是 數(shù)據(jù)接口:I2C， SPI 參考類型:內(nèi)部 電壓 - 電源，模擬:3.14 V ~ 3.46 V 電壓 - 電源，數(shù)字:2.25 V ~ 3.46 V INL/DNL（LSB）:- 架構(gòu):三角積分 工作溫度:-40°C ~ 125°C 封裝/外殼:80-LQFP 供應(yīng)商器件封裝:80-LQFP（14x14） 標準包裝:90 |
發(fā)布緊急采購，3分鐘左右您將得到回復。