參數(shù)資料
型號： ADAU1961WBCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 22/76頁
文件大?。?/td> 0K
描述： IC STEREO AUD CODEC LP 32LFCSP
標(biāo)準(zhǔn)包裝： 1
類型： 音頻編解碼器
數(shù)據(jù)接口： I²C，串行，SPI?
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 無
S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： 98 / 98
動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 96 / 98
電壓 - 電源，模擬： 2.97 V ~ 3.63 V
電壓 - 電源，數(shù)字： 2.97 V ~ 3.63 V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-EP（5x5）
包裝： 托盤
Data Sheet
ADAU1961
Rev. A | Page 29 of 76
Digital Microphone Input
When using a digital microphone connected to the JACKDET/
MICIN pin, the JDFUNC[1:0] bits in Register R2 (Address 0x4008)
must be set to 10 to enable the microphone input and disable
the jack detection function. The ADAU1961 must operate in
master mode and source BCLK to the input clock of the digital
microphone.
The digital microphone signal bypasses record path mixers and
ADCs and is routed directly into the decimation filters. The
digital microphone and ADCs share decimation filters and,
therefore, both cannot be used simultaneously. The digital
microphone input select bit, INSEL, can be set in Register R19
(ADC control register, Address 0x4019). Figure 35 depicts the
digital microphone interface and signal routing.
JDFUNC[1:0]
DIGITAL MICROPHONE
INTERFACE
LEFT
CHANNEL
RIGHT
CHANNEL
TO JACK
DETECTION
CIRCUIT
JACKDET/MICIN
RIGHT
ADC
LEFT
ADC
DECIMATORS
R19: ADC CONTROL
INSEL
R2: DIGITAL MICROPHONE/
JACK DETECTION
CONTROL
08915-
023
Figure 35. Digital Microphone Interface Block Diagram
Microphone Bias
The MICBIAS pin provides a voltage reference for electret analog
microphones. The MICBIAS voltage is set in Register R10
(record microphone bias control register, Address 0x4010). In
this register, the MICBIAS output can be enabled or disabled.
Additional options include high performance operation and a
gain boost. The gain boost provides two different voltage biases:
0.65 × AVDD or 0.90 × AVDD. When enabled, the high perfor-
mance bit increases supply current to the microphone bias
circuit to decrease rms input noise.
The MICBIAS pin can also be used to cleanly supply voltage
to digital microphones or analog microphones with separate
power supply pins.
ANALOG-TO-DIGITAL CONVERTERS
The ADAU1961 uses two 24-bit Σ-Δ analog-to-digital con-
verters (ADCs) with selectable oversampling ratios of 64× or
128× (selected by Bit 3 in Register R17, Address 0x4017).
ADC Full-Scale Level
The full-scale input to the ADCs (0 dBFS) is 1.0 V rms with
AVDD = 3.3 V. This full-scale analog input will output a digital
signal at 1.38 dBFS. This gain offset is built into the ADAU1961
to prevent clipping. The full-scale input level scales linearly with
the level of AVDD.
For single-ended and pseudo-differential signals, the full-scale
value corresponds to the signal level at the pins, 0 dBFS.
The full differential full-scale input level is measured after the
differential amplifier, which corresponds to 6 dBFS at each pin.
Signal levels above the full-scale value cause the ADCs to clip.
Digital ADC Volume Control
The digital ADC volume can be attenuated using Register R20 (left
input digital volume register, Address 0x401A) and Register R21
(right input digital volume register, Address 0x401B).
High-Pass Filter
By default, a high-pass filter is used in the ADC path to remove
dc offsets; this filter can be enabled or disabled in Register R19
(ADC control register, Address 0x4019). At fS = 48 kHz, the
corner frequency of this high-pass filter is 2 Hz.
相關(guān)PDF資料
PDF描述
MC908GZ60MFJE IC MCU 8BIT 60K FLASH 32-LQFP
MC908GZ32VFJE IC MCU 8BIT 32K FLASH 32-LQFP
AD74111YRUZ IC CODEC AUDIO MONO LP 16TSSOP
VI-22R-IY-F3 CONVERTER MOD DC/DC 7.5V 50W
CS4270-CZZ IC CODEC 24BIT 105DB 24TSSOP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADAU1961WBCPZ-R7 功能描述:IC STEREO AUD CODEC LP 32LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
ADAU1961WBCPZ-RL 功能描述:IC STEREO AUD CODEC LP 32LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
ADAU1962AWBSTZ 制造商:Analog Devices 功能描述:AUTOMOTIVE HIGH PERFORMANCE 12 DAC - Trays 制造商:Analog Devices 功能描述:IC DAC 80LQFP 制造商:Analog Devices 功能描述:DAC 24 BITS 48KHZ SPI LQFP 制造商:Analog Devices 功能描述:DAC, 24BIT, 192KSPS, LQFP-80, Resolution (Bits):24bit, Sampling Rate:192kSPS, Input Channel Type:Differential, Single Ended, Supply Voltage Range:3.14V to 3.46V, Digital IC Case Style:LQFP, No. of Pins:80, Data Interface:I2C, SPI
ADAU1962AWBSTZ-RL 功能描述:24 Bit Digital to Analog Converter 12 80-LQFP (14x14) 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):有效 位數(shù):24 數(shù)模轉(zhuǎn)換器數(shù):12 建立時(shí)間:- 輸出類型:Voltage - Unbuffered 差分輸出:是 數(shù)據(jù)接口:I2C， SPI 參考類型:內(nèi)部 電壓 - 電源，模擬:3.14 V ~ 3.46 V 電壓 - 電源，數(shù)字:2.25 V ~ 3.46 V INL/DNL（LSB）:- 架構(gòu):三角積分 工作溫度:-40°C ~ 125°C 封裝/外殼:80-LQFP 供應(yīng)商器件封裝:80-LQFP（14x14） 標(biāo)準(zhǔn)包裝:1,000
ADAU1962WBSTZ 功能描述:24 Bit Digital to Analog Converter 12 80-LQFP (14x14) 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):有效 位數(shù):24 數(shù)模轉(zhuǎn)換器數(shù):12 建立時(shí)間:- 輸出類型:Voltage - Unbuffered 差分輸出:是 數(shù)據(jù)接口:I2C， SPI 參考類型:內(nèi)部 電壓 - 電源，模擬:3.14 V ~ 3.46 V 電壓 - 電源，數(shù)字:2.25 V ~ 3.46 V INL/DNL（LSB）:- 架構(gòu):三角積分 工作溫度:-40°C ~ 125°C 封裝/外殼:80-LQFP 供應(yīng)商器件封裝:80-LQFP（14x14） 標(biāo)準(zhǔn)包裝:90
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*