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      參數(shù)資料
      型號: ADAU1382BCPZ-R7
      廠商: ANALOG DEVICES INC
      元件分類: 消費(fèi)家電
      英文描述: SPECIALTY CONSUMER CIRCUIT, PQCC32
      封裝: 5 X 5 MM, ROHS COMPLIANT, MO-220VHHD2, LFCSP-32
      文件頁數(shù): 60/84頁
      文件大?。?/td> 1193K
      代理商: ADAU1382BCPZ-R7
      ADAU1382
      Rev. 0| Page 63 of 84
      PLAYBACK PATH CONFIGURATION
      Register 16412 (0x401C), Playback Mixer Left Control
      Bit 5, Left DAC Mute
      This bit mutes the left DAC output. It does not have any slew
      and is updated immediately when the register write has been
      completed. This results in an abrupt cutoff of the audio output
      and should therefore be preceded by a soft mute in the sound
      engine or a slew mute using the DAC attenuator.
      Bits[4:1], Left Playback Beep Gain
      These bits set the gain of the beep signal in the left playback
      path. If the zero-crossing detector is activated, the change in
      gain is applied on the next detected zero crossing or when the
      timeout period expires, whichever comes first. The gain control
      is in 3 dB increments and should not be incremented more than
      3 dB at a time in order to avoid audible artifacts on the output.
      Register 16414 (0x401E), Playback Mixer Right Control
      Bit 6, Right DAC Mute
      This bit mutes the right DAC output. It does not have any slew
      and is updated immediately when the register write has been
      completed. This results in an abrupt cutoff of the audio output
      and should therefore be preceded by a soft mute in the sound
      engine or a slew mute using the DAC attenuator.
      Bits[4:1], Right Playback Beep Gain
      These bits set the gain of the beep signal in the right playback
      path. If the zero-crossing detector is activated, the change in
      gain is applied on the next detected zero crossing or when the
      timeout period expires, whichever comes first. The gain control
      is in 3 dB increments and should not be incremented more than
      3 dB at a time in order to avoid audible artifacts on the output.
      Table 47. Playback Mixer Left Control Register
      Bits
      Description
      Default
      [7:6]
      Reserved
      5
      Left DAC mute
      0
      0: muted
      1: unmuted
      [4:1]
      Left playback beep gain
      0000
      0000: muted
      0001: 15 dB
      0010: 12 dB
      0011: 9 dB
      0100: 6 dB
      0101: 3 dB
      0110: 0 dB
      0111: +3 dB
      1000: +6 dB
      0
      Reserved
      Table 48. Playback Mixer Right Control Register
      Bits
      Description
      Default
      7
      Reserved
      6
      Right DAC mute
      0
      0: muted
      1: unmuted
      5
      Reserved
      [4:1]
      Right playback beep gain
      0000
      0000: muted
      0001: 15 dB
      ...
      1000: +6 dB
      0
      Reserved
      相關(guān)PDF資料
      PDF描述
      ADAU1382BCPZ SPECIALTY CONSUMER CIRCUIT, PQCC32
      ADC-00403-103 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP32
      ADC0831 A/D Peripherals with Serial Control
      ADC0831A A/D Peripherals with Serial Control
      ADC0831B A/D Peripherals with Serial Control
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