參數(shù)資料
型號： ADAU1381BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 28/84頁
文件大?。?/td> 0K
描述： IC AUDIO CODEC STEREO LN 32LFCSP
標準包裝： 1
類型： 立體聲音頻
數(shù)據(jù)接口： 串行，SPI?
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 無
S/N 比，標準 ADC / DAC (db)： 97 / 100
動態(tài)范圍，標準 ADC / DAC (db)： 96.5 / 100
電壓 - 電源，模擬： 1.8 V ~ 3.65 V
電壓 - 電源，數(shù)字： 1.63 V ~ 3.65 V
工作溫度： -25°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ
包裝： 托盤
配用： EVAL-ADAU1381Z-ND - BOARD EVALUATION FOR ADAU1381
ADAU1381
Rev. B | Page 34 of 84
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence
with normal read and write operations, the ADAU1381
immediately jumps to the idle condition. During a given SCL
high period, the user should issue only one start condition, one
stop condition, or a single stop condition followed by a single
start condition. If an invalid subaddress is issued by the user,
the ADAU1381 does not issue an acknowledge and returns to
the idle condition. If the user exceeds the highest subaddress while
in auto-increment mode, one of two actions is taken. In read mode,
the ADAU1381 outputs the highest subaddress register contents
until the master device issues a no acknowledge, indicating the
end of a read. A no-acknowledge condition is where the SDA
line is not pulled low on the ninth clock pulse on SCL. If the
highest subaddress location is reached while in write mode, the
data for the invalid byte is not loaded into any subaddress register,
a no acknowledge is issued by the ADAU1381, and the part returns
to the idle condition.
R/W
0
SCL
SDA
SCL
(CONTINUED)
SDA
(CONTINUED)
11
1
0
ADDR0
ADDR1
START BY
MASTER
FRAME 1
CHIP ADDRESS BYTE
FRAME 2
SUBADDRESS BYTE 1
FRAME 3
SUBADDRESS BYTE 2
FRAME 4
DATA BYTE 1
ACKNOWLEDGE
BY ADAU1381
ACKNOWLEDGE
BY ADAU1381
ACKNOWLEDGE
BY ADAU1381
ACKNOWLEDGE
BY ADAU1381
STOP BY
MASTER
0
83
13
-03
6
Figure 38. I2C Write to ADAU1381 Clocking
SCL
SDA
SCL
(CONTINUED)
SDA
(CONTINUED)
SCL
(CONTINUED)
SDA
(CONTINUED)
START BY
MASTER
ACKNOWLEDGE
BY ADAU1381
ACKNOWLEDGE
BY ADAU1381
REPEATED
START BY MASTER
ACKNOWLEDGE
BY ADAU1381
ACKNOWLEDGE
BY ADAU1381
ACKNOWLEDGE
BY MASTER
STOP BY
MASTER
ACKNOWLEDGE
BY ADAU1381
01
1
0
ADDR0
ADDR1
01
1
0
ADDR0
ADDR1
FRAME 1
CHIP ADDRESS BYTE
FRAME 2
SUBADDRESS BYTE 1
FRAME 3
SUBADDRESS BYTE 2
FRAME 4
CHIP ADDRESS BYTE
FRAME 5
READ DATA BYTE 1
FRAME 6
READ DATA BYTE 2
R/W
08
31
3-
03
7
Figure 39. I2C Read from ADAU1381 Clocking
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