參數(shù)資料
型號: ADAU1381BCPZ-RL7
廠商: Analog Devices Inc
文件頁數(shù): 74/84頁
文件大小: 0K
描述: IC AUDIO CODEC STEREO LN 32LFCSP
標(biāo)準(zhǔn)包裝: 1,500
類型: 立體聲音頻
數(shù)據(jù)接口: 串行,SPI?
分辨率(位): 24 b
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變:
S/N 比,標(biāo)準(zhǔn) ADC / DAC (db): 97 / 100
動態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 96.5 / 100
電壓 - 電源,模擬: 1.8 V ~ 3.65 V
電壓 - 電源,數(shù)字: 1.63 V ~ 3.65 V
工作溫度: -25°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 32-LFCSP-VQ
包裝: 帶卷 (TR)
配用: EVAL-ADAU1381Z-ND - BOARD EVALUATION FOR ADAU1381
ADAU1381
Rev. B | Page 76 of 84
Register 16434 (0x4032), Dejitter Control
Bits[7:0], Dejitter Window Size
The dejitter control register not only allows the size of the
dejitter window to be set, but also allows all dejitter circuits in
the device to be activated or bypassed. Dejitter circuits protect
against duplicate samples or skipped samples due to jitter from
the serial ports in slave mode. Disabling and reenabling certain
subsystems in the device—that is, the ADCs, serial ports, sound
engine/DSP core, and DACs—during operation can cause the
associated dejitter circuits to fail. As a result, audio data fails to
be output to the next subsystem in the device.
When the serial ports are in master mode, the dejitter circuit
can be bypassed by setting the dejitter window to 0. When the
serial ports are in slave mode, the dejitter circuit can be reinitialized
prior to outputting audio from the device, guaranteeing that audio
is output to the next subsystem in the device. Any time audio
needs to pass through the ADCs, serial port, sound engine/DSP
core, or DACs, the dejitter circuit can be bypassed and reset by
setting the dejitter window size to 0. Then, the dejitter circuit can
be immediately reactivated, without a wait period, by setting the
dejitter window size to the default value of 5.
Table 64. Dejitter Control Register
Bits
Description
Default
[7:0]
Dejitter window size
00000101
00000000: 0 core clock cycles
00000101: 5 core clock cycles
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