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參數(shù)資料
| 型號(hào)： | ADAU1373BCBZ-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 235/296頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CODEC LP W/HDPH AMP 81WLSCP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 音頻編解碼器 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 分辨率（位）： | 24 b |
| ADC / DAC 數(shù)量： | 1 / 2 |
| 三角積分調(diào)變： | 是 |
| S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： | 96 / 96 |
| 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： | 96 / 96 |
| 電壓 - 電源，模擬： | 1.62 V ~ 1.98 V |
| 電壓 - 電源，數(shù)字： | 1.08 V ~ 1.98 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 81-UFBGA，WLCSP |
| 供應(yīng)商設(shè)備封裝： | 81-WLCSP（4.05x3.82） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ADAU1373BCBZ-R7DKR |
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ADAU1373
Rev. 0 | Page 43 of 296
HEADPHONE OUTPUT
The ADAU1373 provides a high efficiency Class-G stereo
headphone output that is true ground centered; therefore,
no external coupling capacitors are required for connection to
the headphones. The headphones can be connected directly to
the headphone output pins, HPL (Ball G8) and HPR (Ball G9).
The headphone amplifier uses the supply provided at HPVDD
(Ball H8). The recommended operating supply voltage is 1.8 V.
This supply voltage must be decoupled with a 1 μF electrolytic
capacitor, along with a 100 nF ceramic X7R capacitor. The
headphone amplifier uses Class-G architecture and generates the
required power supplies, using a flying capacitor with a built-in
charge pump connected across CF1 (Ball J9) and CF2 (Ball J7).
The charge pump switching frequency is approximately 500 kHz.
The generated supply voltages are available at CPVDD (Ball H9,
positive rail), and CPVSS (Ball H7, negative rail).
The voltage at this node depends on the input signal to the
amplifier. For lower input signal levels, the positive and negative
rails are lowered, typically ±0.9 V for 1.8 V HPVDD. As the
signal level increases, CPVDD and CPVSS are raised to a higher
voltage of ±1.8 V for 1.8 V HPVDD. This rail switching allows
the amplifier to achieve higher efficiency. In most typical usage
conditions, the amplifier works on the lower ±0.9 V CPVDD and
CPVSS voltages, thereby consuming lower power. In addition, as
the amplifier generates the positive and negative rails, the output
amplifier is true ground centered, thereby eliminating the need for
big coupling capacitors to drive the load. For good audio per-
formance, it is recommended that 1 μF, X7R ceramic decoupling
capacitors be used for CPVDD and CPVSS. These capacitors
serve as a reservoir for the headphone amplifier.
The amplifier has built-in short-circuit protection and,
therefore, shuts down in the event of a short circuit on the
headphone outputs.
SGND (Ball G7) is provided for sensing the dc potential at the
headphone socket. It is recommended that SGND be connected
directly to the ground pin of the headphone socket, which ensures
the lowest dc offset at the amplifier output and eliminates pop-
and-click turn on/turn off for the amplifier. In addition, it helps
reduce crosstalk between the left and right channel outputs.
The headphone amplifier is designed to drive headphones with
a minimum impedance of 16 Ω. The output level of the amplifier
can be controlled using Register 0x0F (left channel headphone
output volume control bits) and Register 0x10 (right channel
headphone output volume control bits).
In addition, the headphone amplifier can be set to different
working modes, depending on the performance and power
consumption requirements (Register 0x1D, Bits[3:2]). The
available modes include Class-G (default), high efficiency, and
low efficiency. In Class-G mode, the amplifier rails are switched
between ±0.9 V and ±1.8 V, depending on the signal level. The
threshold for rail switching in Class-G operation can be set to
300 mV, 400 mV, or 500 mV using Register 0x1E, Bits[6:5].
In high efficiency mode, the rails are fixed at ±0.9 V, independent
of the input signal level. This mode reduces the output power
available from the amplifier and also reduces the amount of
current consumed by the battery.
In low efficiency mode, the rails are fixed at ±1.8 V, independent
of the input signal level. This mode enables the amplifier to
produce higher output levels, but current consumption is higher
than in high efficiency mode.
It is recommended that the default mode, Class-G mode, be used
because the supply rails are switched based on the input level.
The headphone amplifier also has a built-in overcurrent
protection circuit that protects the amplifier against a short
circuit to ground on the outputs. The overcurrent detect threshold
level can be programmed to the desired load impedance level
using Register 0x1D, Bits[1:0]. The available settings are 200 mA,
250 mA, 300 mA, and 350 mA.
The turn on time for the headphone amplifier is programmable
using Register 0x1D, Bits[5:4]. Four settings are available: 2 ms,
4 ms, 8 ms, and 16 ms.
The headphone jack insertion detect feature can be used to turn
off the speaker amplifier when the headphones are connected to
the amplifier, thereby saving extra power consumed from the
battery. Register 0x36, Bits[1:0] and Register 0x38, Bit 4 are
provided to turn on this feature. Note that this feature requires
the use of a headphone jack with a switch. See Figure 89 for
more information.
JACKDET
ADAU1373
HEADPHONE
JACK
100k
TYP
≥ AVDD
HPL
HPR
SGND
08
975-
029
Figure 89. Headphone Jack Detect Option 1
In a typical application, the headphone amplifier is powered down,
and its output is typically high impedance when inactive. Using
Register 0x1E, Bit 4 (HIZ), the headphone outputs can be pulled
down with a 300 Ω resistor. When set to a lower impedance, the
JACKDET pin (Ball G5) is pulled to ground via the 300 Ω internal
resistance of the headphone amplifier. When the headphone plug
is inserted into the headphone socket, the switch at the tip of the
socket is disconnected. This, in turn, pulls the JACKDET pin
to logic high via Resistor R1. This change in logic level at the
JACKDET pin can be used to initiate the interrupt on the GPIOx
pin or can be read in the IRQ status register (Register 0xE7), Bit 1
(HP_DECT_STATUS).
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| ADAU1373BCBZ-RL | 功能描述:IC CODEC LP CLASS G HP 81WLCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
| ADAU1381 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Noise Stereo Codec with Enhanced Recording and Playback Processing |
| ADAU1381BCBZ-RL | 功能描述:IC AUDIO CODEC STEREO LN 30WLCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
| ADAU1381BCBZ-RL7 | 功能描述:IC AUDIO CODEC STEREO LN 30WLCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
| ADAU1381BCPZ | 功能描述:IC AUDIO CODEC STEREO LN 32LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
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