By default, the ADAU1361 is in I2C mode, but i" />
參數(shù)資料
型號： ADAU1361BCPZ-RL
廠商： Analog Devices Inc
文件頁數(shù)： 36/80頁
文件大小： 0K
描述： IC CODEC 24B PLL 32LFCSP
標(biāo)準(zhǔn)包裝： 5,000
類型： 音頻編解碼器
數(shù)據(jù)接口： 串行
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 無
電壓 - 電源，模擬： 1.8 V ~ 3.6 V
電壓 - 電源，數(shù)字： 1.8 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ
包裝： 帶卷 (TR)
ADAU1361
Rev. C | Page 41 of 80
SPI PORT
By default, the ADAU1361 is in I2C mode, but it can be put into
SPI control mode by pulling CLATCH low three times. This is
done by performing three dummy writes to the SPI port (the
ADAU1361 does not acknowledge these three writes). Beginning
with the fourth SPI write, data can be written to or read from
the IC. The ADAU1361 can be taken out of SPI mode only by
a full reset initiated by power-cycling the IC.
The SPI port uses a 4-wire interface, consisting of the CLATCH,
CCLK, CDATA, and COUT signals, and it is always a slave port.
The CLATCH signal should go low at the beginning of a trans-
action and high at the end of a transaction. The CCLK signal
latches CDATA on a low-to-high transition. COUT data is shifted
out of the ADAU1361 on the falling edge of CCLK and should
be clocked into a receiving device, such as a microcontroller, on
the CCLK rising edge. The CDATA signal carries the serial input
data, and the COUT signal carries the serial output data. The
COUT signal remains three-state until a read operation is requested.
This allows other SPI-compatible peripherals to share the same
readback line. All SPI transactions have the same basic format
shown in
. A timing diagram is shown in
. All
data should be written MSB first.
Chip Address R/W
The LSB of the first byte of an SPI transaction is a R/W bit. This bit
determines whether the communication is a read (Logic Level 1)
or a write (Logic Level 0). This format is shown in
Table 22. ADAU1361 SPI Address and Read/Write Byte Format
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
0
R/W
Subaddress
The 16-bit subaddress word is decoded into a location in one of
the registers. This subaddress is the location of the appropriate
register. The MSBs of the subaddress are zero-padded to bring
the word to a full 2-byte length.
Data Bytes
The number of data bytes varies according to the register being
accessed. During a burst mode write, an initial subaddress is
written followed by a continuous sequence of data for consecu-
tive register locations.
A sample timing diagram for a single-word SPI write operation
to a register is shown in Figure 54. A sample timing diagram of
a single-word SPI read operation is shown in Figure 55. The
COUT pin goes from being three-state to being driven at the
beginning of Byte 3. In this example, Byte 0 to Byte 2 contain
the addresses and R/W bit, and subsequent bytes carry the data.
Table 23. Generic Control Word Format
Byte 0
Byte 1
Byte 2
Byte 3
Byte 41
chip_adr[6:0], R/W
subaddr[15:8]
subaddr[7:0]
data
1 Continues to end of data.
07
67
9-
0
38
CLATCH
CCLK
CDATA
BYTE 0
BYTE 1
BYTE 2
BYTE 3
Figure 54. SPI Write to ADAU1361 Clocking (Single-Word Write Mode)
07
67
9-
03
9
CLATCH
CCLK
CDATA
COUT
BYTE 0
BYTE 1
HIGH-Z
DATA
HIGH-Z
BYTE 2
Figure 55. SPI Read from ADAU1361 Clocking (Single-Word Read Mode)
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