參數(shù)資料
型號(hào): ADATE302-02BBCZ
廠(chǎng)商: Analog Devices Inc
文件頁(yè)數(shù): 52/58頁(yè)
文件大小: 0K
描述: IC DCL ATE 500MHZ DUAL 84CSPBGA
標(biāo)準(zhǔn)包裝: 1
類(lèi)型: DCL
應(yīng)用: 自動(dòng)測(cè)試設(shè)備
安裝類(lèi)型: 表面貼裝
封裝/外殼: 84-TFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 84-CSPBGA(9x9)
包裝: 托盤(pán)
ADATE302-02
Rev. A | Page 56 of 58
PMU
V/I CLAMP
FLAG
–2.5V
OVD LOW LEVEL
DAC (ADDR[4:0] = 0x0A, CH[0])
(ADDR[4:0] = 0x12) DATA[1]
PMU MASK ENABLES PMU V/I
FLAG TO ALARM OVD_CHx PIN
ADATE302-02
(ADDR[4:0] = 0x12) DATA[0]
OVD MASK ENABLES OVD
FLAGS TO ALARM OVD_CHx PIN
OVD_CHx
SHORT CIRCUIT
CURRENT = 100A
(ADDR[4:0] = 0x13) 2 DATA[2] DATA[1] DATA[0]
1THE OVD HIGH/LOW LEVEL DAC IS SHARED BY EACH CHANNEL; THEREFORE, ONLY ONE OVD HIGH/LOW VOLTAGE
LEVEL CAN BE SET PER CHIP. THE OVD DACs PROVIDE A VOLTAGE RANGE OF –3V TO +7V. THE RECOMMENDED
HIGH/LOW SETTINGS ARE +6.5V/–2.5V. (THESE VALUES NEED TO BE PROGRAMMED BY THE USER UPON STARTUP/RESET.)
2THIS IS A READ ONLY REGISTER THAT ALLOWS THE USER TO DETERMINE THE CAUSE OF THE ACTIVE OVD FLAG.
6.5V
OVD HIGH LEVEL
DAC (ADDR[4:0] = 0x0A, CH[1])
DUT
1
07
27
8-
01
9
Figure 93. OVD Block Diagram
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