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| 型號： | ADATE302-02BBCZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 40/58頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DCL ATE 500MHZ DUAL 84CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | DCL |
| 應(yīng)用： | 自動(dòng)測試設(shè)備 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 84-TFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 84-CSPBGA（9x9） |
| 包裝： | 托盤 |
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ADATE302-02
Rev. A | Page 45 of 58
DETAILS OF REGISTERS
Table 22. PE/PMU Enable (ADDR[4:0] = 0x0C)
Bit
Name
Description
Data[2]
PMU enable
0 = disable PMU force output and clamps, place PMU in MV mode
1 = enable PMU force output
When set to 0, the PMU State bits are ignored, except for PMU Sense Path (Data[7]).
Data[1]
Force VT
0 = normal driver operation
1 = force driver to VT
See Table 30 for complete functionality of this bit.
Data[0]
PE disable
0 = enable driver functions
1 = disable driver (low leakage)
See Table 30 for complete functionality of this bit.
Table 23. Channel State (ADDR[4:0] = 0x0D)
Bit
Name
Description
Data[2]
HVOUT mode select
0 = HVOUT driver in low impedance
1 = enable HVOUT driver
This bit affects Channel 0 only. Ensure that Channel 0 bit in SPI write is active.
Channel 1 bit in SPI write is don’t care.
Data[1]
Load enable
0 = disable load
1 = enable load
See Table 30 for complete functionality of this bit.
Data[0]
Driver high-Z/VT
0 = enable driver high-Z function
1 = enable driver VTERM function
See Table 30 for complete functionality of this bit.
Table 24. PMU State (ADDR[4:0] = 0x0E)1, 2
Bit
Name
Description
Data[9:8]
PMU input selection
00 = VDUTGND (calibrated for 0.0 V voltage reference)
01 = 2.5 V + VDUTGND (calibrated for 0.0 A current reference)
1X = PMUDAC
Data[7]
PMU sense path
0 = internal sense
1 = external sense
Data[6]
Reserved
Data[5]
PMU clamp enable
0 = disable clamps
1 = enable clamps
Data[4]
PMU measure V/I
0 = measure voltage mode
1 = measure current mode
Data[3]
PMU force V/I
0 = force voltage mode
1 = force current mode
Data[2:0]
PMU range
0XX = Range E (2 μA)
100 = Range D (20 μA)
101 = Range C (200 μA)
110 = Range B (2 mA)
111 = Range A (25 mA)
1 Note that when the ADDR[4:0] = 0x0C PMU enable bit (Data[2]) = 0, the PMU force outputs and clamps are disabled, and the PMU is placed into measure voltage
mode. Data[9:8] and Data[6:0] of the PMU state register are ignored, and only Data[7], the PMU sense path bit, is valid.
2 X = don’t care.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADATE302-02BSVZ | 功能描述:IC DCL ATE 500MHZ DUAL 100TQFP RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| ADATE302BBCZ-02 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| ADATE302BSVZ | 制造商:Analog Devices 功能描述: |
| ADATE303BBCZ | 制造商:Analog Devices 功能描述: |
| ADATE304 | 制造商:AD 制造商全稱:Analog Devices 功能描述:200 MHz Dual Integrated DCL with Level Setting DACs, Per Pin PMU, and Per Chip VHH |
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