參數(shù)資料
型號: ADADC71KD
廠商: Analog Devices Inc
文件頁數(shù): 4/12頁
文件大?。?/td> 0K
描述: IC ADC 16BIT HIGH RES 32-CDIP
標準包裝: 1
位數(shù): 16
采樣率(每秒): 20k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 850mW
電壓電源: 雙 ±
工作溫度: 0°C ~ 70°C
安裝類型: 通孔
封裝/外殼: 32-CDIP(0.900",22.86mm)
供應商設(shè)備封裝: 32-CDIP 底部銅焊
包裝: 管件
輸入數(shù)目和類型: 2 個單端,單極;2 個單端,雙極
ADADC71
Rev. C | Page 12 of 12
OUTLINE DIMENSIONS
NOTES:
1. INDEX AREA IS INDICATED BY A NOTCH OR LEAD ONE
IDENTIFICATION MARK LOCATED ADJACENT TO LEAD ONE.
2. CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
0.023 (0.58)
0.014 (0.36)
0.910 (23.11)
0.890 (22.61)
1
16
17
32
1.728 (43.89) MAX
0.225 (5.72)
MAX
0.025 (0.64)
0.015 (0.38)
0.008 (0.20)
1.102 (27.99)
1.079 (27.41)
0.100 (2.54)
BSC
0.070 (1.78)
0.030 (0.76)
0.120 (3.05)
MAX
PIN 1
INDICATOR
(NOTE 1)
0.192 (4.88)
0.152 (3.86)
0.206 (5.23)
0.186 (4.72)
0.025 (0.64)
MIN
Figure 14. 32-Lead Bottom-Brazed Ceramic Dip for Hybrid [BBDIP_H]
(DH-32E)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model
Linearity Error (Max)
Specification Temp Range
Package Option
AD ADC71JD
±0.006% of FSR
0°C to +70°C
Ceramic (DH-32E)
AD ADC71KD
±0.003% of FSR
0°C to +70°C
Ceramic (DH-32E)
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03537–0–6/05(C)
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