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參數(shù)資料
| 型號(hào)： | ADADC71KD |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 3/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT HIGH RES 32-CDIP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 20k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 850mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 32-CDIP（0.900"，22.86mm） |
| 供應(yīng)商設(shè)備封裝： | 32-CDIP 底部銅焊 |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個(gè)單端，單極；2 個(gè)單端，雙極 |
ADADC71
Rev. C | Page 11 of 12
USING THE ADADC71 AT SLOWER CONVERSION
TIMES
The user may wish to run the ADADC71 at slower conversion
times in order to synchronize the ADC with an external clock.
This is accomplished by running a slower clock that the internal
clock into the START CONVERT input. This clock must consist
of narrow negative-going clock pulses, as seen in Figure 13. The
pulse must be a minimum of 100 ns wide, but not greater than
700 ns. Having a raising edge immediately after a falling edge
inhibits the internal clock pulse. This enables the ADADC71 to
function normally and complete a conversion after 16 clock
pulses. The STATUS command functions normally and
switches high after the first clock pulse and falls low after the
17th clock pulse. In this way an external clock can be used to
control the ADADC71 at slower conversion times.
03537-
013
START CONVERT
(EXTERNAL CLOCK)
CLOCK OUT
STATUS
100ns MIN
1500ns MAX1
t1
t15
t16
t0
NOTE:
1EXTENAL CLK RATE CTRL (PIN 23) GROUNDED.
Figure 13. Timing Diagram for Use with an External Clock
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