參數(shù)資料
型號(hào)： ADA4424-6ARUZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 4/16頁(yè)
文件大?。?/td> 0K
描述： IC FILTR VID6CH SD/ED/HD 38TSSOP
標(biāo)準(zhǔn)包裝： 50
濾波器類型： SD/ED/HD
濾波器數(shù)： 6
濾波器階數(shù)： 5th
電源電壓： 3.3V，5V
安裝類型： 表面貼裝
封裝/外殼： 38-TFSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 38-TSSOP
包裝： 管件
產(chǎn)品目錄頁(yè)面： 776 (CN2011-ZH PDF)
ADA4424-6
Rev. C | Page 12 of 16
Fixed Offset Cancellation Mode
In addition to the automatic mode, there are two levels of fixed
offset correction available. In high offset mode, fixed voltages of
1.0 V and 1.1 V are subtracted from the Y_IN and HY_IN inputs,
respectively. In low offset mode, a fixed voltage of 0.33 V is
subtracted from both Y_IN and HY_IN. The various modes of
offset cancellation are outlined in Table 6.
Table 6. Offset Cancellation Mode Selection
MODE1
(Pin 23)
MODE0
(Pin 16)
Output Offset Cancellation
Low (0)
Auto-cancel, sync-tip sampling mode.
Clamps the input referred SD sync tip
to 214 mV, and the input referred
ED/HD sync tip to 300 mV.
Low (0)
High (1)
Auto-cancel, back porch sampling
mode. Sets the output blanking level
to 0 V, independent of sync depth.
High (1)
Low (0)
Fixed cancellation mode, high dc
offset.
Subtracts 1.0 V from the Y_IN signal;
subtracts 1.1 V from the HY_IN signal.
High (1)
Fixed cancellation mode, low dc offset.
Subtracts 0.33 V from both the Y_IN
and HY_IN signals.
Offset Cancellation Disable
The offset cancellation function can be enabled or disabled via
the OFFSET_ENB pin, as described in Table 7.
Table 7. Offset Cancellation Enable/Disable
OFFSET_ENB
(Pin 17)
Offset Cancellation State
Low (0)
Offset cancellation is disabled.
High (1)
Offset cancellation is enabled. Function is
determined by the MODE1 and MODE0 pins
(see Table 6).
D-TERMINAL AND S-TERMINAL SUPPORT
Full D-terminal support (EIAJ RC-5237 D5) is provided for the
component channels (HY_OUT, HPb_OUT, HPr_OUT). Level
D1 through Level D5 are supported for vertical resolution, scan
type, and aspect ratio selection. Details are shown in Table 8,
S-terminal (also known as S_DC or S1/S2) support for S-video
aspect ratio selection is also provided, as described in Table 11.
The VDD5 pin (Pin 38) provides 5 V power for these outputs.
If D- or S-terminal support is not required, it is recommended
that Pin 2 to Pin 5 and Pin 34 to Pin 38 remain unconnected.
Table 8. D-Terminal Control for Vertical Resolution Selection
Input Logic
Level D1 (Pin 2)
Nominal Output (V)
L1_OUT (Pin 37)
RL = 100 kΩ
Vertical Resolution
(Number of Lines)
Low (0)
0.0
480
Mid or open
2.1
720
High (1)
4.5
1080
Table 9. D-Terminal Control for Scan Selection
Input Logic Level
D2 (Pin 3)
Nominal Output (V)
L2_OUT (Pin 36)
RL = 100 kΩ
Scan Type
Low (0)
0.0
Interlaced
Mid or open
2.1
N/A
High (1)
4.5
Progressive
Table 10. D-Terminal Control for Aspect Ratio Selection
Input Logic Level
D3 (Pin 4)
Nominal Output (V)
L3_OUT (Pin 35)
RL = 100 kΩ
Aspect Ratio
Low (0)
0.0
4:3
Mid or open
2.1
4:3 letterbox
High (1)
4.5
16:9
Table 11. S-Terminal Control for Aspect Ratio Selection
Input Logic Level
S (Pin 5)
Nominal Output (V)
S1/S2_OUT (Pin 34)
RL = 100 kΩ
Aspect Ratio
Low (0)
0.0
4:3
Mid or open
2.1
4:3 letterbox
High (1)
4.5
16:9
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