參數(shù)資料
型號： ADA4424-6ARUZ
廠商： Analog Devices Inc
文件頁數(shù)： 11/16頁
文件大?。?/td> 0K
描述： IC FILTR VID6CH SD/ED/HD 38TSSOP
標準包裝： 50
濾波器類型： SD/ED/HD
濾波器數(shù)： 6
濾波器階數(shù)： 5th
電源電壓： 3.3V，5V
安裝類型： 表面貼裝
封裝/外殼： 38-TFSOP（0.173"，4.40mm 寬）
供應商設備封裝： 38-TSSOP
包裝： 管件
產品目錄頁面： 776 (CN2011-ZH PDF)
ADA4424-6
Rev. C | Page 4 of 16
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
Quiescent Supply Current, 5 V Supply
SD_ENABLE = high, HD_ENABLE = high,
RL = 100 kΩ, D1, D2, D3 = high, S = high
190
200
μA
SD_ENABLE = low, HD_ENABLE = low
5
15
μA
PSRR
ED/HD channels, output referred
42
dB
SD channels, output referred
41
dB
DC Offset
Input Referred, Offset Cancellation
Disabled Mode
OFFSET_ENB = low
SD Channels
Y_IN = 0 V dc
60
20
+60
mV
CVBS Channel
Y_IN = 0 V dc
100
40
+100
mV
ED/HD Channels
HY_IN = 0 V dc
60
20
+60
mV
Input Referred, Fixed Offset
Cancellation Mode
OFFSET_ENB = high, MODE1 = high
SD Fixed High Offset Mode
Y_IN = 1.0 V dc, MODE0 = low
100
30
+100
mV
ED/HD Fixed High Offset Mode
HY_IN = 1.1 V dc, MODE0 = low
100
38
+100
mV
SD Fixed Low Offset Mode
Y_IN = 0.33 V dc, MODE0 = high
90
17
+90
mV
ED/HD Fixed Low Offset Mode
HY_IN = 0.33 V dc, MODE0 = high
100
25
+100
mV
Input Referred, Auto Offset
Cancellation Mode
OFFSET_ENB = high, MODE1 = low
SD Auto Offset Mode
Sync Tip Sampling
Y_IN = 0 V to 1.0 V dc, MODE0 = low
70
36
+70
mV
ED/HD Auto Offset Mode
Sync Tip Sampling
HY_IN = 0 V to 1.1 V dc, MODE0 = low
95
46
+95
mV
SD Auto Offset Mode
Back Porch Sampling
Y_IN = 0 V to 1.0 V dc, MODE0 = high
25
6
+25
mV
ED/HD Auto Offset Mode
Back Porch Sampling
HY_IN = 0 V to 1.1 V dc, MODE0 = high
25
5
+25
mV
FC_SEL Input Logic Low Level
0
0.6
V
FC_SEL Input Logic High Level
1.2
VDD3
V
xD_ENABLE, OFFSET_ENB, MODEx
Input Logic Low Level
0
0.8
V
xD_ENABLE, OFFSET_ENB, MODEx
Input Logic High Level
2.0
VDD3
V
xD_ENABLE Assert Time
xD_ENABLE = low to high
95
ns
xD_ENABLE Deassert Time
xD_ENABLE = high to low
20
ns
xD_ENABLE Input Bias Current
Disabled, xD_ENABLE = low
6.1
μA
Input-to-Output Isolation
Disabled, xD_ENABLE = low, f = 5 MHz
100
dB
D- and S-Terminal Input Logic
Low Level
RL = 100 kΩ
0
0.6
V
D- and S-Terminal Input Logic
Mid Level
RL = 100 kΩ
0.9
1.9
V
D- and S-Terminal Input Logic
High Level
RL = 100 kΩ
2.7
VDD3
V
D- and S-Terminal Input Logic Open
(Hi-Z) Resistance Value
RL = 100 kΩ
200
kΩ
D-Terminal (L1_OUT, L2_OUT, L3_OUT)
Low Level Output
VDD5 = 5.0 V, RL = 100 kΩ, D1, D2, D3 = low
0.0
V
D-Terminal (L1_OUT, L3_OUT) Mid
Level Output
VDD5 = 5.0 V, RL = 100 kΩ, D1, D3 = mid or open
2.1
V
D-Terminal (L1_OUT, L2_OUT, L3_OUT)
High Level Output
VDD5 = 5.0 V, RL = 100 kΩ, D1, D2, D3 = high
4.5
V
S-Terminal (S1/S2_OUT) Low Level
Output
VDD5 = 5.0 V, RL = 100 kΩ, S = low
0.0
V
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