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參數(shù)資料
| 型號： | AD9959 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | 4 Channel 500MSPS DDS with 10-bit DACs |
| 中文描述： | DDS的4通道500MSPS的10位DAC |
| 文件頁數(shù)： | 8/9頁 |
| 文件大?。?/td> | 225K |
| 代理商： | AD9959 |
AD9959
Preliminary Technical Data
Table 3. Pin Function Descriptions
Pin No.
1
2
3
Rev. PrB | Page 8 of 9
Mnemonic
SYNC_IN
SYNC_OUT
MASTER_RESET
PWR_DWN_CTL
AVDD
I/O
I
O
I
Description
Used to synchronize multiple AD9959s. Connect to the SYNC_OUT pin of the master AD9959.
Used to synchronize multiple AD9959s. Connect to the SYNC_IN pin of the slave AD9959.
Active high reset pin. Asserting the RESET pin forces the AD9959’s internal registers to their
default state, as described in the serial I/O port register map section in this document.
External Power-Down Control.
Analog Power Supply Pins (1.8V).
4
5,7,11,15,19,21,
26,31,33,37,39
6,10,12,16,18,20,
25,28,32,34,38
45, 55
44, 56
8
I
I
AGND
I
Analog Ground Pins.
DVDD
DGND
CH2_IOUT
_________
CH2_IOUT
CH3_IOUT
_________
CH3_IOUT
DAC_RSET
I
I
O
Digital Power Supply Pins (1.8 V).
Digital Power Ground Pins.
True DAC Output. Terminate into AVDD.
9
O
Complementary DAC Output. Terminate into AVDD.
13
O
True DAC Output. Terminate into AVDD.
14
O
Complementary DAC Output. Terminate into AVDD.
17
I
Establishes the reference current for all DACs. A 1.962 k resistor (nominal) is connected from
pin 17 to AGND.
Complementary Reference Clock/Oscillator Input. When the REF_CLK is operated in single-
ended mode, this pin should be decoupled to AVDD or AGND with a 0.1 μF capacitor.
Reference Clock/Oscillator Input. When the REF_CLK is operated in single-ended mode, this is
the input.
Control Pin for the Oscillator Section. When high (1.8V), the oscillator section is enabled to
accept a crystal as the REFCLK source. When low, the oscillator section is bypassed.
CAUTION: Do not drive this pin beyond 1.8V.
Connect to the external zero compensation network of the PLL loop filter for the REFCLK
multiplier. For a 20x multiplier value the network should be a 1.2k resistor in series with a 1.2
nF capacitor tied to AVDD.
22
OSC / REF_CLK
I
23
OSC / REF_CLK
I
24
CLK_MODE_SEL
I
27
LOOP_FILTER
I
29
_________
CH0_IOUT
CH0_IOUT
_________
CH1_IOUT
CH1_IOUT
PS0, PS1,
PS2, PS3
O
Complementary DAC Output. Terminate into AVDD.
30
O
True DAC Output. Terminate into AVDD.
35
O
Complementary DAC Output. Terminate into AVDD.
36
40, 41,
42, 43
O
I
True DAC Output. Terminate into AVDD.
These Pins are synchronous to the SYNC_CLK (pin 54). Any change in Profile inputs transfers
the contents of the internal buffer memory to the I/O active registers (same as an external I/O
_UPDATE).
A rising edge detected on this pin transfers data from serial port buffer to active registers.
Active low chip select allowing multiple devices to share a common I/O bus (SPI).
Serial data clock for I/O operations. Data bits are written on rising edge of SCLK and read on
the falling edge of SCLK.
3.3 V Digital Power Supply for SPI port and I/O (excluding CLK_MODE_SEL).
These data pins have multiple functions. Data I/O pins for the serial I/O port operation. They
are also used as data pins in modulation modes
.
I/O_UPDATE and Profile signals should meet the set-up and hold requirements with respect to
this signal in order to guarantee a fixed pipeline delay of data to DAC outputs.
46
47
48
I/O_UPDATE
CS
SCLK
I
I
I
49
50, 51
52, 53
54
DVDD_I/O
SDIO_0, SDIO_1
SDIO_2, SDIO_3
SYNC_CLK
I
I/O
O
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9959/PCBZ | 功能描述:BOARD EVALUATION FOR AD9959 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9959/PCBZ | 制造商:Analog Devices 功能描述:AD9959, DDS, DAC, GUI, USB, EVALUATION B |
| AD9959/PCBZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 500 MSPS DDS with 10-Bit DACs |
| AD9959_08 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 500 MSPS DDS with 10-Bit DACs |
| AD9959BCPZ | 功能描述:IC DDS QUAD 10BIT DAC 56LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
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