參數(shù)資料
型號: AD9959
廠商: Analog Devices, Inc.
元件分類: XO, clock
英文描述: 4 Channel 500MSPS DDS with 10-bit DACs
中文描述: DDS的4通道500MSPS的10位DAC
文件頁數(shù): 4/9頁
文件大小: 225K
代理商: AD9959
AD9959
Preliminary Technical Data
Rev. PrB | Page 4 of 9
Maximum Clock Rise/Fall Time
Minimum Data Setup Time (t
DS
)
Minimum Data Hold Time
MISC TIMING CHARACTERISTICS
Master_Reset minimum Pulsewidth
I/O_Update minimum Pulsewidth
Minimum setup time (IO_Update to Sync_CLK)
Minimum hold time (IO_Update to Sync_CLK)
Minimum setup time (Profile inputs to Sync_CLK)
Minimum hold time (Profile inputs to Sync_CLK)
DATA LATENCY (PIPE LINE DELAY)
TBD
TBD
TBD
ns
ns
ns
TBD
1
TBD
0
TBD
0
Sync CLK
Sync CLK
ns
ns
ns
ns
Rising edge to rising edge
Rising edge to rising edge
Pipeline delays for Freq, Phase,
Amp changes are programmable to
match one another.
matched
unmatched
unmatched
unmatched
Matched pipe line of Freq, Phase, Amplitude
Frequency word to DAC output
Phase Offset word to DAC output
Amplitude word to DAC output
CMOS LOGIC INPUTS
TBD
TBD
TBD
TBD
Sys Clks
Sys Clks
Sys Clks
Sys Clks
V
IH
V
IL
Logic 1 Current
Logic 0 Current
Input Capacitance
2.2
-12
V
V
uA
uA
pF
0.6
12
3
2
CMOS LOGIC OUTPUTS (1 mA Load)
V
OH
V
OL
POWER SUPPLY
Total Power Dissipation- all channels ON, single-tone mode
Maximum Power Dissipation- all channels, freq accumulator
output multiplier ON
Iavdd – All Channels ON, Single tone mode
Iavdd – All Ch(s) ON, Freq accum, and output multiplier ON
Idvdd – All Ch(s) ON, Single tone mode
Idvdd – All Ch(s) ON, Freq accum, and output multiplier ON
Idvdd_I/O
Power down Mode
2.8
V
V
0.4
TBD
TBD
mW
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
mA
mA
mA
mA
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