參數(shù)資料
型號(hào)： AD9850BRS-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 16/20頁(yè)
文件大?。?/td> 0K
描述： IC DDS SYNTHESIZER CMOS 28-SSOP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝： 1,500
分辨率（位）： 10 b
主 fclk： 125MHz
調(diào)節(jié)字寬（位）： 32 b
電源電壓： 3.3V，5V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 28-SSOP
包裝： 帶卷 (TR)
AD9850
–5–
REV. H
PIN CONFIGURATION
17
16
15
20
19
18
28
27
26
25
24
23
22
21
14
13
12
11
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
AD9850
D3
D7 MSB/SERIAL LOAD
D6
D5
D4
D2
D1
LSB D0
RESET
DVDD
DGND
DVDD
W CLK
FQ UD
CLKIN
AGND
IOUTB
IOUT
AVDD
RSET
QOUTB
QOUT
AVDD
VINN
VINP
DACBL (NC)
NC = NO CONNECT
Table I. PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Function
4 to 1,
D0 to D7
8-Bit Data Input. This is the 8-bit data port for iteratively loading the 32-bit frequency and the 8-bit phase/
28 to 25
control word. D7 = MSB; D0 = LSB. D7 (Pin 25) also serves as the input pin for the 40-bit serial data-word.
5, 24
DGND
Digital Ground. These are the ground return leads for the digital circuitry.
6, 23
DVDD
Supply Voltage Leads for Digital Circuitry.
7W_CLK
Word Load Clock. This clock is used to load the parallel or serial frequency/phase/control words.
8
FQ_UD
Frequency Update. On the rising edge of this clock, the DDS updates to the frequency (or phase)
loaded in the data input register; it then resets the pointer to Word 0.
9
CLKIN
Reference Clock Input. This may be a continuous CMOS-level pulse train or sine input biased at
1/2 V supply. The rising edge of this clock initiates operation.
10, 19
AGND
Analog Ground. These leads are the ground return for the analog circuitry (DAC and comparator).
11, 18
AVDD
Supply Voltage for the Analog Circuitry (DAC and Comparator).
12
RSET
DAC’s External RSET Connection. This resistor value sets the DAC full-scale output current. For
normal applications (FS IOUT = 10 mA), the value for RSET is 3.9 k
connected to ground. The R
SET/IOUT
relationship is IOUT = 32 (1.248 V/RSET).
13
QOUTB
Output Complement. This is the comparator’s complement output.
14
QOUT
Output True. This is the comparator’s true output.
15
VINN
Inverting Voltage Input. This is the comparator’s negative input.
16
VINP
Noninverting Voltage Input. This is the comparator’s positive input.
17
DACBL (NC)
DAC Baseline. This is the DAC baseline voltage reference; this lead is internally bypassed and should
normally be considered a no connect for optimum performance.
20
IOUTB
Complementary Analog Output of the DAC.
21
IOUT
Analog Current Output of the DAC.
22
RESET
Reset. This is the master reset function; when set high, it clears all registers (except the input register), and
the DAC output goes to cosine 0 after additional clock cycles—see Figure 7.
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