參數(shù)資料
型號(hào)： AD9847AKSTZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 7/28頁(yè)
文件大?。?/td> 0K
描述： IC CCD SIGNAL PROC 10BIT 48-LQFP
標(biāo)準(zhǔn)包裝： 1
類型： CCD 信號(hào)處理器，10 位
輸入類型： 邏輯
輸出類型： 邏輯
接口： 3 線串口
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 托盤
REV. A
AD9847
–15–
Bit
Default
Address
Content
Width
Value
Register Name
Register Description
AFE Register Breakdown
Serial Address:
oprmode
[7:0]
8'h0
8'h00 {oprmode[5:0]}, 8'h01 {oprmode[7:6]}
[1:0]
2'h0
powerdown[1:0]
Full Power
2'h1
Fast Recovery
2'h2
Reference Standby
2'h3
Total Shutdown
[2]
disblack
Disable Black Loop Clamping (High Active)
[3]
test mode
Test Mode—Should Be Set Low
[4]
test mode
Test Mode—Should Be Set High
[5]
test mode
Test Mode—Should Be Set Low
[6]
test mode
Test Mode—Should Be Set Low
[7]
test mode
Test Mode—Should Be Set Low
ctlmode
[5:0]
6'h0
Serial Address: 8'h06 {cltmode[5:0]}
[2:0]
3'h0
ctlmode[2:0]
Off
3'h1
Mosaic Separate
3'h2
VD Selected/Mosaic Interlaced
3'h3
Mosaic Repeat
3'h4
Three-Color
3'h5
Three-Color II
3'h6
Four-Color
3'h7
Four-Color II
[3]
enablepxga
Enable PxGA (High Active)
[4]
1'h0
outputlat
Latch Output Data on Selected DOUT Edge
1'h1
Leave Output Latch Transparent
[5]
1'h0
tristateout
ADC Outputs Are Driven
1'h1
ADC Outputs Are Three-Stated
PRECISION TIMING HIGH SPEED TIMING
GENERATION
The AD9847 generates flexible high speed timing signals using
the Precision Timing core. This core is the foundation for generating
the timing used for both the CCD and the AFE, the reset gate RG,
horizontal drivers H1–H4, and the SHP/SHD sample clocks.
A unique architecture makes it routine for the system designer to
optimize image quality by providing precise control over the hori-
zontal CCD readout and the AFE correlated double sampling.
NOTES
1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.
2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (
t
CLIDLY = 6 ns TYP).
P[0]
P[48]=P[0]
P[12]
P[24]
P[36]
1 PIXEL
PERIOD
...
CLI
tCLIDLY
POSITION
Figure 4. High Speed Clock Resolution from CLI Master Clock Input
Timing Resolution
The Precision Timing core uses a 1
master clock input (CLI) as
a reference. This clock should be the same as the CCD pixel clock
frequency. Figure 4 illustrates how the internal timing core
divides the master clock period into 48 steps or edge positions.
Therefore, the edge resolution of the Precision Timing core is
(tCLI /48). For more information on using the CLI input, see the
Applications Information section.
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參數(shù)描述
AD9847AKSTZRL 功能描述:IC CCD SIGNAL PROC 10BIT 48-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測(cè)器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件
AD9847KST 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:
ad9847kstrl 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel 制造商:Analog Devices 功能描述:
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