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參數(shù)資料
| 型號： | AD9847AKSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SIGNAL PROC 10BIT 48-LQFP |
| 標準包裝： | 1 |
| 類型： | CCD 信號處理器，10 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
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REV. A
AD9847
–18–
(3)
(2)
(1)
HD
CLPOB
CLPDM
PBLK
. . .
NOTES
PROGRAMMABLE SETTINGS:
(1) START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW)
(2) FIRST TOGGLE POSITION
(3) SECOND TOGGLE POSITION
. . .
CLAMP
Figure 9. Clamp and Preblank Pulse Placement
(2)
(1)
HD
HBLK
. . .
NOTES
PROGRAMMABLE SETTINGS:
(1) FIRST TOGGLE POSITION = START OF BLANKING
(2) SECOND TOGGLE POSITION = END OF BLANKING
. . .
BLANK
Figure 10. Horizontal Blanking (HBLK) Pulse Placement
Table IV. CLPOB, CLPDM, PBLK Individual Sequence Parameters
Register Name
Length
Range
Description
SPOL
1b
High/Low
Starting Polarity of Clamp and Blanking Pulses for Sequences 0–3
TOG1
12b
0–4095 Pixel Location
First Toggle Position within the Line for Sequences 0–3
TOG2
12b
0–4095 Pixel Location
Second Toggle Position within the Line for Sequences 0–3
Table V. HBLK Individual Sequence Parameters
Register Name
Length
Range
Description
HBLKMASK
1b
High/Low
Masking Polarity for H1 for Sequences 0–3 (0 = H1 Low, 1 = H1 High)
HBLKTOG1
12b
0–4095 Pixel Location
First Toggle Position within the Line for Sequences 0–3
HBLKTOG2
12b
0–4095 Pixel Location
Second Toggle Position within the Line for Sequences 0–3
HORIZONTAL CLAMPING AND BLANKING
The AD9847’s horizontal clamping and blanking pulses are fully
programmable to suit a variety of applications. As with the vertical
timing generation, individual sequences are defined for each
signal and are then organized into multiple regions during image
readout. This allows the dark pixel clamping and blanking patterns
to be changed at each stage of the readout, in order to accom-
modate different image transfer timing and high speed line shifts.
Individual CLPOB, CLPDM, and PBLK Sequences
The AFE horizontal timing consists of CLPOB, CLPDM, and
PBLK, as shown in Figure 9. These three signals are indepen-
dently programmed using the registers in Table IV. SPOL is the
start polarity for the signal, and TOG1 and TOG2 are the first
and second toggle positions of the pulse. All three signals are
active low and should be programmed accordingly. Up to four
individual sequences can be created for each signal.
Individual HBLK Sequences
The HBLK programmable timing shown in Figure 10 is similar to
CLPOB, CLPDM, and PBLK. However, there is no start polarity
control. Only the toggle positions are used to designate the start
and the stop positions of the blanking period. Additionally, there
is a polarity control, HBLKMASK, that designates the polarity of
the horizontal clock signals H1–H4 during the blanking period.
Setting HBLKMASK high will set H1 = H3 = low and H2 =
H4 = high during the blanking, as shown in Figure 11. Up to
four individual sequences are available for HBLK.
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| AD9847AKSTZRL | 功能描述:IC CCD SIGNAL PROC 10BIT 48-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關文件:Automotive Product Guide 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:20-TSSOP 包裝:管件 |
| AD9847KST | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| ad9847kstrl | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel 制造商:Analog Devices 功能描述: |
| AD9848 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CCD Signal Processors with Integrated Timing Driver |
| AD9848AKST | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3V/3.3V 48-Pin LQFP 制造商:Analog Devices 功能描述:AFE VID 1ADC 10-BIT 3V/3V/3.3V/3.3V/3.3V/3.3V/3.3V 48LQFP - Bulk 制造商:Rochester Electronics LLC 功能描述:10 BIT 20 MSPS CCD SIGNAL PROCESSOR - Tape and Reel |
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