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參數(shù)資料
| 型號(hào)： | AD9844 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete 12-Bit 20 MSPS CCD Signal Processor |
| 中文描述： | 完整的12位20 MSPS的CCD信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 7/16頁(yè) |
| 文件大?。?/td> | 169K |
| 代理商： | AD9844 |
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AD9844A
–7–
REV. 0
DEFINITIONS OF SPECIFICATIONS
DIFFERENTIAL NONLINEARITY (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus every code
must have a finite width. No missing codes guaranteed to 12-bit
resolution indicates that all 4096 codes, respectively, must be
present over all operating conditions.
PEAK NONLINEARITY
Peak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD9844A from a true straight
line. The point used as “zero scale” occurs 1/2 LSB before the
first code transition. “Positive full scale” is defined as a Level
1, 1/2 LSB beyond the last code transition. The deviation is mea-
sured from the middle of each particular output code to the
true straight line. The error is then expressed as a percentage of the
2 V ADC full-scale signal. The input signal is always appropriately
gained up to fill the ADC’s full-scale range.
TOTAL OUTPUT NOISE
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB, and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage, using the relationship 1 LSB
= (ADC Full Scale/2
N
codes) when N is the bit resolution of the
ADC. For the AD9844A, 1 LSB is 0.5 mV.
POWER SUPPLY REJECTION (PSR)
The PSR is measured with a step change applied to the supply
pins. This represents a very high-frequency disturbance on the
AD9844A’s power supply. The PSR specification is calcu-
lated from the change in the data outputs for a given step
change in the supply voltage.
INTERNAL DELAY FOR SHP/SHD
The internal delay (also called aperture delay) is the time delay
that occurs from when a sampling edge is applied to the AD9844A
until the actual sample of the input signal is held. Both SHP and
SHD sample the input signal during the transition from low to
high, so the internal delay is measured from each clock’s rising
edge to the instant the actual internal sample is taken.
EQUIVALENT INPUT CIRCUITS
330
DVDD
DVSS
Figure 1. Digital Inputs—SHP, SHD, DATACLK, CLPOB,
CLPDM, HD, VD, PBLK, SCK, SL
DVDD
DVSS
DRVSS
DRVDD
THREE-
STATE
DATA
DOUT
Figure 2. Data Outputs
ACVDD
ACVSS
ACVSS
Figure 3. CCDIN (Pin 30)
330
DVDD
DVDD
DVSS
DATA IN
RNW
DATA OUT
DVSS
DVSS
Figure 4. SDATA (Pin 47)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9844A | Complete 12-Bit 20 MSPS CCD Signal Processor |
| AD9844AJST | Complete 12-Bit 20 MSPS CCD Signal Processor |
| AD9845B | Complete 12-Bit 30 MSPS CCD Signal Processor |
| AD9845BJST | Complete 12-Bit 30 MSPS CCD Signal Processor |
| AD9845 | Complete 12-Bit 30 MSPS CCD Signal Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9844A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 12-Bit 20 MSPS CCD Signal Processor |
| AD9844AJST | 制造商:Analog Devices 功能描述:AFE Video 1ADC 12-Bit 3.3V 48-Pin LQFP 制造商:Analog Devices 功能描述:AFE VID 1ADC 12-BIT 3.3V 48LQFP - Bulk 制造商:Rochester Electronics LLC 功能描述:12 BIT 20 MHZ ANALOG FRONT END - Tape and Reel |
| AD9844AJSTRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 12-Bit 3.3V 48-Pin LQFP T/R 制造商:Analog Devices 功能描述:AFE VID 1ADC 12-BIT 3.3V 48LQFP - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:12 BIT 20 MHZ ANALOG FRONT END - Tape and Reel |
| AD9844AJSTZ | 制造商:Analog Devices 功能描述:AFE Video 1ADC 12-Bit 3.3V 48-Pin LQFP 制造商:Analog Devices 功能描述:12 BIT 20 MHz ANALOG FRONT END |
| AD9844-EB | 制造商:Analog Devices 功能描述: |
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