參數(shù)資料
型號(hào)： AD9834BRUZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/32頁(yè)
文件大小： 0K
描述： IC DDS 10BIT 50MHZ LP 20TSSOP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計(jì)資源： Amplitude Control Circuit for AD9834 Waveform Generator (CN0156)
標(biāo)準(zhǔn)包裝： 1,000
分辨率（位）： 10 b
主 fclk： 50MHz
調(diào)節(jié)字寬（位）： 28 b
電源電壓： 2.3 V ~ 5.5 V
工作溫度： -40°C ~ 105°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 帶卷 (TR)
Data Sheet
AD9834
The AD9834 is a sampled signal with its output following
Nyquist sampling theorem. Specifically, its output spectrum
contains the fundamental plus aliased signals (images) that
occur at multiples of the reference clock frequency and the
selected output frequency. A graphical representation of the
sampled spectrum, with aliased images, is shown in Figure 28.
The prominence of the aliased images is dependent on the ratio
of fOUT to MCLK. If ratio is small, the aliased images are very
prominent and of a relatively high energy level as determined
by the sin(x)/x roll-off of the quantized DAC output. In fact,
depending on the fOUT/reference clock relationship, the first
aliased image can be on the order of 3 dB below the
fundamental.
A low-pass filter is generally placed between the output of the
DAC and the input of the comparator to further suppress the
effects of aliased images. Obviously, consideration must be
given to the relationship of the selected output frequency and
the reference clock frequency to avoid unwanted (and unexpected)
output anomalies. To apply the AD9834 as a clock generator,
limit the selected output frequency to <33% of reference clock
frequency, and thereby avoid generating aliased signals that fall
within, or close to, the output band of interest (generally dc-
selected output frequency). This practice eases the complexity
(and cost) of the external filter requirement for the clock
generator application. Refer to the AN-837 Application Note
for more information.
To enable the comparator, Bit SIGN/PIB and Bit OPBITEN in
the control resister are set to 1. This is explained further in
REGULATOR
The AD9834 has separate power supplies for the analog and
digital sections. AVDD provides the power supply required for
the analog section, and DVDD provides the power supply for
the digital section. Both of these supplies can have a value of
2.3 V to 5.5 V and are independent of each other. For example,
the analog section can be operated at 5 V, and the digital section
can be operated at 3 V, or vice versa.
The internal digital section of the AD9834 is operated at 2.5 V.
An on-board regulator steps down the voltage applied at DVDD
to 2.5 V. The digital interface (serial port) of the AD9834 also
operates from DVDD. These digital signals are level shifted
within the AD9834 to make them 2.5 V compatible.
When the applied voltage at the DVDD pin of the AD9834 is
equal to or less than 2.7 V, Pin CAP/2.5V and Pin DVDD should
be tied together, thus bypassing the on-board regulator.
OUTPUT VOLTAGE COMPLIANCE
The AD9834 has a maximum current density, set by the RSET,
of 4 mA. The maximum output voltage from the AD9834 is
VDD 1.5 V. This is to ensure that the output impedance of
the internal switch does not change, affecting the spectral
performance of the part. For a minimum supply of 2.3 V, the
maximum output voltage is 0.8 V. Specifications in Table 1 are
guaranteed with an RSET of 6.8 k and an RLOAD of 200 .
02705-
040
SYSTEM CLOCK
fOUT
fC – fOUT
fC + fOUT
2
fC – fOUT
2
fC + fOUT
3
fC – fOUT
3
fC + fOUT
fC
0Hz
FIRST
IMAGE
SECOND
IMAGE
THIRD
IMAGE
FOURTH
IMAGE
FIFTH
IMAGE
SIXTH
IMAGE
2
fC
3
fC
FREQUENCY (Hz)
S
IGN
A
L
A
M
P
LITU
D
E
sin x/x ENVELOPE
x = π (f/fC)
Figure 28. The DAC Output Spectrum
Rev. D | Page 17 of 32
相關(guān)PDF資料
PDF描述
VE-B1H-IW-B1 CONVERTER MOD DC/DC 52V 100W
VE-B1F-IX-B1 CONVERTER MOD DC/DC 72V 75W
MCF51AC256BCPUE MCU 32BIT 256K FLASH 64-LQFP
AD9834BRUZ-REEL IC DDS 10BIT 50MHZ LP 20TSSOP
MCF51EM256CLK IC MCU 32BIT 256KB FLASH 80LQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9834CRUZ 功能描述:IC DDS 10BIT 75MHZ LP 20-TSSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
AD9834CRUZ-REEL7 功能描述:IC DDS 10BIT 75MHZ LP 20-TSSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
AD9835 制造商:AD 制造商全稱:Analog Devices 功能描述:50 MHz CMOS Complete DDS
AD9835BRU 功能描述:IC DDS DAC 10BIT 50MHZ 16-TSSOP RoHS:否 類(lèi)別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
AD9835BRU-REEL 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 50MHz 1-DAC 10-Bit Serial 16-Pin TSSOP T/R 制造商:Analog Devices 功能描述:DGTL SYNTHESIZER 16TSSOP - Tape and Reel
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*