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參數(shù)資料
| 型號： | AD9834 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low Power, +2.3 V to +5.5 V, 50 MHz Complete DDS |
| 中文描述： | 低功耗，2.3 V至5.5 V，50 MHz的完整的DDS |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 236K |
| 代理商： | AD9834 |
AD9834
–
9
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REV PrM
PRELIMINARY TECHNICAL DATA
CIRCUIT DESCRIPTION
The AD9834 is a fully integrated Direct Digital Synthesis
(DDS) chip. The chip requires one reference clock, one
low precision resistor and eight decoupling capacitors to
provide digitally created sine waves up to 25 MHz. In
addition to the generation of this RF signal, the chip is
fully capable of a broad range of simple and complex
modulation schemes. These modulation schemes are fully
implemented in the digital domain allowing accurate and
simple realization of complex modulation algorithms us-
ing DSP techniques.
The internal circuitry of the AD9834 consists of the fol-
lowing main sections: a Numerical Controlled Oscillator
(NCO), Frequency and Phase Modulators, SIN ROM, a
Digital-to-Analog Converter, a Comparator and a
Regulator.
Numerical Controlled Oscillator + Phase Modulator
This consists of two frequency select registers, a phase
accumulator, two phase offset registers and a phase offset
adder. The main component of the NCO is a 28-bit phase
accumulator which assembles the phase component of the
output signal. Continuous time signals have a phase range
of 0 to 2 . Outside this range of numbers, the sinusoid
functions repeat themselves in a periodic manner. The
digital implementation is no different. The accumulator
simply scales the range of phase numbers into a multibit
digital word. The phase accumulator in the AD9834 is
implemented with 28 bits. Therefore, in the AD9834, 2
= 2
28
. Likewise, the
Phase
term is scaled into this range
of numbers 0 <
Phase
< 2
28
– 1. Making these substitu-
tions into the equation above
f
=
Phase
x
f
MCLK
/2
28
where 0 <
Phase
< 2
28
- 1.
The input to the phase accumulator (i.e., the phase step)
can be selected either from the FREQ0 Register or
FREQ1 Register and this is controlled by the FSELECT
pin or the FSEL bit. NCOs inherently generate
continuous phase signals, thus avoiding any output
discontinuity when switching between frequencies.
Following the NCO, a phase offset can be added to
perform phase modulation using the 12-bit Phase
Registers. The contents of one of these phase registers is
added to the most significant bits of the NCO. The
AD9834 has two Phase registers, the resolution of these
registers being 2
π
/4096.
SIN ROM
To make the output from the NCO useful, it must be
converted from phase information into a sinusoidal value.
Since phase information maps directly into amplitude, the
SIN ROM uses the digital phase information as an ad-
dress to a look-up table, and converts the phase
information into amplitude. Although the NCO contains a
28-bit phase accumulator, the output of the NCO is trun-
cated to 12 bits. Using the full resolution of the phase
accumulator is impractical and unnecessary as this would
require a look-up table of 2
28
entries. It is necessary only
to have sufficient phase resolution such that the errors due
to truncation are smaller than the resolution of the 10-bit
DAC. This requires the SIN ROM to have two bits of
phase resolution more than the 10-bit DAC.
The SIN ROM is enabled using bits MODE and
OPBITEN in the control register. This is explained fur-
ther in Table 14.
Digital-to-Analog Converter
The AD9834 includes a high impedance current source
10-bit DAC, capable of driving a wide range of loads.
Full-scale output current can be adjusted, for optimum
power and external load requirements, through the use of
a single external resistor (R
SET
).
The DAC can be configured for either single-ended or
differential operation. IOUT and IOUTB can be con-
nected through equal external resistors to AGND to
develop complementary output voltages. The load resis-
tors can be any value required, as long as the full-scale
voltage developed across it does not exceed the voltage
compliance range. Since full-scale current is controlled by
R
SET
, adjustments to R
SET
can balance changes made to the
load resistors.
Comparator
The AD9834 can be used to generate synthesised digital
clock signals. This can be done by using the on-board
self-biasing comparator, which converts the DAC's sinu-
soidal signal to a square wave. The output from the DAC
may be filtered externally before being applied to the
comparator input. The comparator reference voltage is the
time-average of the signal applied to V
IN
. The comparator
can accept a signal of 1 Vpp. As the comparator's input is
ac-coupled, to operate correctly as a zero crossing
dectector, it requires a minimum input frequency of 3
MHz. The comparator's output will be a square wave with
an amplitude from 0 V to DVDD.
To enable the comparator, bits SIGNPIB and OPBITEN
in the control resister are set to '1'. This is explained fur-
ther in Table 13.
Regulator
The AD9834 has separate power supplies for the analog
and digital section. AVDD provides the power supply
required for the analog section, while DVDD provides the
power supply for the digital section. Both of these supplies
can have a value of +2.3V to +5.5V, and are independant
of each other e.g. the analog section can be operated at 5V
and the digital section can be operated at 3V or vice versa.
The internal digital section of the AD9834 is operated at
2.5 V. An on-board regulator steps down the voltage ap-
plied at DVDD to 2.5 V. The digital inteface (serial port)
of the AD9834 is also operated from DVDD. These digi-
tal signals are level shifted within the AD9834 to make
them 2.5V compatible.
When the applied voltage at the DVDD pin of the
AD9834 is equal to or less than 2.5V, the pins CAP/2.5V
and DVDD should be tied together, thus by-passing the
on-board regulator.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9834_10 | 制造商:AD 制造商全稱:Analog Devices 功能描述:20 mW Power, 2.3 V to 5.5 V,75 MHz Complete DDS |
| AD9834BRU | 功能描述:IC DDS W/COMP 2.3V 50MHZ 20TSSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9834BRU-REEL | 功能描述:IC DDS 10BIT 50MHZ LP 20-TSSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9834BRU-REEL7 | 功能描述:IC DDS 10BIT 50MHZ LP 20-TSSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9834BRUZ | 功能描述:IC DDS 10BIT 50MHZ LP 20-TSSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
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