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參數(shù)資料
| 型號： | AD9816 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete 12-Bit 6 MSPS CCD/CIS Signal Processor(12位的采樣速率為6MSPS的CCD/CIS信號處理器) |
| 中文描述： | 完整的12位6 MSPS的防治荒漠化公約/ CIS信號處理器（12位的采樣速率為6MSPS的防治荒漠化公約/獨聯(lián)體信號處理器） |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 190K |
| 代理商： | AD9816 |
AD9816
–13–
REV. A
Analog-to-Digital Converter
The AD9816 uses a high speed 12-bit ADC core. This CMOS
converter is designed to run at 6 MSPS with good linearity and
noise performance. Figure 19 shows the INL and DNL perfor-
mance of a typical AD9816 device, running at 6 MHz in 3-channel
CDS mode using the timing shown in Figure 1. The following
timing parameters were used: t
CRA
= 500 ns, t
ADCLK
= 83 ns,
t
C1
= 20 ns, t
C1C2
= 170 ns, t
C1
= 80 ns, t
ADC2
= 3 ns, t
C2AD
= 83ns,
and t
C2C1
= 230 ns.
The digital outputs of the AD9816 follow a straight binary
coding scheme. Table VI shows the digital output coding for
the 3 V input span.
0.2
0.0
–0.2
–0.4
–0.6
–0.8
–1.2
–1.4
–1.6
0
4095
I
1200
400
1600
800
1.0
0.5
–1.0
1.5
D
2000
2400
2800
3200
3600
0.0
–0.5
0
4095
1200
400
1600
800
2000
2400
2800
3200
3600
MAX INL 0.18
MAX DNL 0.31
Figure 19. Typical Linearity Performance
Table VI. Digital Output Format
Input Voltage
1
Digital Outputs
3.0 – 1 LSB
3.0 – 2 LSB
0.0 + 1 LSB
0.0
1111 1111 1111
1111 1111 1110
0000 0000 0001
0000 0000 0000
NOTE
1
Analog input voltage in CDS mode is the difference between the
CCD’s reference and data levels.
3:1
DIFF
MUX
RED
GREEN
BLUE
PGA
PGA
PGA
SELECT
MUX
CONTROL
2
ADCCLK
CDSCLK2
12-BIT ADC
PGAOUT_T
PGAOUT_C
Figure 17. PGA/MUX Circuit Configuration
ANALOG
INPUTS
CDSCLK2
ADCCLK
PGAOUT_T
PGAOUT_C
PIXEL n
BLUE
GREEN
RED
RESET
GREEN(n–1)
BLUE(n–1)
RED(n)
GREEN(n)
BLUE(n)
RESET
4.25V
3.5V
2.75V
Figure 18. PGA Output Voltages (ADC Input Range = 3 V)
Table V. Voltage Swing of PGA Outputs
Analog
Input
Voltage
1
Differential
ADC
Input
PGAOUT_T
PGAOUT_C
0.00
2
1.50
2
3.00
2
0.00
3
0.75
3
1.50
3
2.75
3.50
4.25
3.125
3.50
3.875
4.25
3.50
2.75
3.875
3.50
3.125
1.5
0.0
+1.5
0.75
0.0
+0.75
NOTES
1
Analog input voltage in CDS mode is the difference between the CCD’s refer-
ence and data levels.
2
3.0 V Input Range.
3
1.5 V Input Range.
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD9821 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 12-Bit 40 MSPS Imaging Signal Processor |
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