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參數(shù)資料
| 型號： | AD9814JRRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SIGNAL PROC 14BIT 28-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | CCD 信號處理器，14 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 80mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
REV. 0
AD9814
–11–
PGA Gain Registers
There are three PGA registers for individually programming the gain in the red, green and blue channels. Bits D8, D7 and D6 in
each register must be set low, and bits D5 through D0 control the gain range in 64 increments. See Figure 13 for a graph of the PGA
Gain versus PGA register code. The coding for the PGA registers is straight binary, with an all “zeros” word corresponding to the
minimum gain setting (1x) and an all “ones” word corresponding to the maximum gain setting (5.8x).
Table IV. PGA Gain Register Settings
D8
D7
D6
D5
D4
D3
D2
D1
D0
Gain (V/V)
Gain (dB)
Set to 0
MSB
LSB
0
0*
1.0
0.0
0
1
1.013
0.12
0
1
0
5.4
14.6
0
1
5.8
15.25
*Power-on default value.
Offset Registers
There are three PGA registers for individually programming the offset in the red, green and blue channels. Bits D8 through D0 con-
trol the offset range from –300 mV to +300 mV in 512 increments. The coding for the offset registers is sign magnitude, with D8 as
the sign bit. Table V shows the offset range as a function of the Bits D8 through D0.
Table V. Offset Register Settings
D8
D7
D6
D5
D4
D3
D2
D1
D0
Offset (mV)
MSB
LSB
000000000*
0
000000001+1.2
011111111
+300
1000000000
100000001
–1.2
111111111
–300
*Power-on default value.
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| AD9814KR | 制造商:Analog Devices 功能描述:AFE Video 1ADC 14-Bit 5V 28-Pin SOIC W 制造商:Analog Devices 功能描述:14 BIT 6 MSPS SCANNER ANALOG FRONT END - Rail/Tube 制造商:Rochester Electronics LLC 功能描述:14 BIT 6 MSPS SCANNER ANALOG FRONT END - Bulk |
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