- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄11656 > AD9814JRRL (Analog Devices Inc)IC CCD SIGNAL PROC 14BIT 28-SOIC PDF資料下載
參數(shù)資料
| 型號： | AD9814JRRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SIGNAL PROC 14BIT 28-SOIC |
| 標準包裝： | 1,000 |
| 類型： | CCD 信號處理器，14 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 80mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
REV. 0
AD9814
–9–
FUNCTIONAL DESCRIPTION
The AD9814 can be operated in four different modes: 3-Channel
CDS Mode, 3-Channel SHA Mode, 1-Channel CDS Mode,
and 1-Channel SHA Mode. Each mode is selected by program-
ming the Configuration Register through the serial interface.
For more detail on CDS or SHA mode operation, see the
Circuit Operation section.
3-Channel CDS Mode
In 3-Channel CDS Mode, the AD9814 simultaneously samples
the red, green and blue input voltages from the CCD outputs.
The sampling points for each Correlated Double Sampler (CDS)
are controlled by CDSCLK1 and CDSCLK2 (see Figures 8 and
9). CDSCLK1’s falling edge samples the reference level of the
CCD waveform. CDSCLK2’s falling edge samples the data
level of the CCD waveform. Each CDS amplifier outputs the
difference between the CCD’s reference and data levels. Next,
the output voltage of each CDS amplifier is level-shifted by an
Offset DAC. The voltages are then scaled by the three Program-
mable Gain Amplifiers before being multiplexed through the
14-bit ADC. The ADC sequentially samples the PGA outputs
on the falling edges of ADCCLK.
The offset and gain values for the red, green and blue channels
are programmed using the serial interface. The order in which
the channels are switched through the multiplexer is selected by
programming the MUX register.
Timing for this mode is shown in Figure 1. It is recommended
that the falling edge of CDSCLK2 occur coincident with or
before the rising edge of ADCCLK, although this is not re-
quired to satisfy the minimum timing constraints. The rising
edge of CDSCLK2 should not occur before the previous falling
edge of ADCCLK, as shown by tADC2. The output data latency
is three clock cycles.
3-Channel SHA Mode
In 3-Channel SHA Mode, the AD9814 simultaneously samples
the red, green and blue input voltages. The sampling point is
controlled by CDSCLK2. CDSCLK2’s falling edge samples the
input waveforms on each channel. The output voltages from the
three SHAs are modified by the offset DACs and then scaled by
the three PGAs. The outputs of the PGAs are then multiplexed
through the 14-bit ADC. The ADC sequentially samples the
PGA outputs on the falling edges of ADCCLK.
The input signal is sampled with respect to the voltage applied
to the OFFSET pin (see Figure 10). With the OFFSET pin
grounded, a zero volt input corresponds to the ADC’s zero-scale
output. The OFFSET pin may also be used as a coarse offset
adjust pin. A voltage applied to this pin will be subtracted from
the voltages applied to the red, green and blue inputs in the first
amplifier stage of the AD9814. The input clamp is disabled in this
mode. For more information, see the Circuit Operation section.
Timing for this mode is shown in Figure 2. CDSCLK1 should
be grounded in this mode. Although not required, it is recom-
mended that the falling edge of CDSCLK2 occur coincident
with or before the rising edge of ADCCLK. The rising edge of
CDSCLK2 should not occur before the previous falling edge of
ADCCLK, as shown by tADC2. The output data latency is three
ADCCLK cycles.
The offset and gain values for the red, green and blue channels
are programmed using the serial interface. The order in which
the channels are switched through the multiplexer is selected by
programming the MUX register.
1-Channel CDS Mode
This mode operates in the same way as the 3-Channel CDS
mode. The difference is that the multiplexer remains fixed in
this mode, so only the channel specified in the MUX register is
processed.
Timing for this mode is shown in Figure 3. Although not re-
quired, it is recommended that the falling edge of CDSCLK2
occur coincident with or before the rising edge of ADCCLK.
1-Channel SHA Mode
This mode operates in the same way as the 3-Channel SHA
mode, except that the multiplexer remains stationary. Only the
channel specified in the MUX register is processed.
The input signal is sampled with respect to the voltage applied
to the OFFSET pin. With the OFFSET pin grounded, a zero
volt input corresponds to the ADC’s zero scale output. The
OFFSET pin may also be used as a coarse offset adjust pin. A
voltage applied to this pin will be subtracted from the voltages
applied to the red, green and blue inputs in the first amplifier
stage of the AD9814. The input clamp is disabled in this mode.
For more information, see the Circuit Operation section.
Timing for this mode is shown in Figure 4. CDSCLK1 should
be grounded in this mode of operation. Although not required,
it is recommended that the falling edge of CDSCLK2 occur
coincident with or before the rising edge of ADCCLK.
相關PDF資料 |
PDF描述 |
|---|---|
| D38999/26JF32SC | CONN PLUG 32POS STRAIGHT W/SCKT |
| CS3100A-24-58S | CONN RCPT 13POS WALL MNT W/SCKT |
| MCR908JK3ECPE | IC MCU FLASH 8BIT RC OSC 20-DIP |
| MS3110P22-21S | CONN RCPT 21POS WALL MNT W/SCKT |
| MC9S08EL16CTJ | MCU 16KB FLASH SLIC 20TSSOP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9814KR | 制造商:Analog Devices 功能描述:AFE Video 1ADC 14-Bit 5V 28-Pin SOIC W 制造商:Analog Devices 功能描述:14 BIT 6 MSPS SCANNER ANALOG FRONT END - Rail/Tube 制造商:Rochester Electronics LLC 功能描述:14 BIT 6 MSPS SCANNER ANALOG FRONT END - Bulk |
| AD9814KRRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 14-Bit 5V 28-Pin SOIC W 制造商:Analog Devices 功能描述:14 BIT 6 MSPS SCANNER ANALOG FRONT END - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:14 BIT 6 MSPS SCANNER ANALOG FRONT END - Bulk |
| AD9814S | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit CCD/CIS Signal Processor |
| AD9816 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 12-Bit 6 MSPS CCD/CIS Signal Processor |
| AD9816-EB | 制造商:Analog Devices 功能描述:12-BIT 4MSPS CCD/CIS SIGNAL PROCESSOR - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。