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參數(shù)資料
| 型號(hào)： | AD9802JST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Silver Mica Capacitor; Capacitance:10pF; Capacitance Tolerance: 5%; Series:CD17; Voltage Rating:500VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:5.9mm; Leaded Process Compatible:Yes RoHS Compliant: Yes |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, TQFP-48 |
| 文件頁(yè)數(shù)： | 9/20頁(yè) |
| 文件大?。?/td> | 366K |
| 代理商： | AD9802JST |
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AD9802
–9–
REV. 0
T he actual implementation of this loop is slightly more compli-
cated as shown in Figure 19. Because there are two separate
CDS blocks, two black level feedback loops are required and
two offset voltages are developed. Figure 19 also shows an addi-
tional PGA block in the feedback loop labeled “RPGA.” T he
RPGA uses the same control inputs as the PGA, but has the
inverse gain. T he RPGA functions to attenuate by the same
factor as the PGA amplifies, keeping the gain and bandwidth of
the loop constant.
T here exists an unavoidable mismatch in the two offset voltages
used to correct both CDS blocks. T his mismatch causes a slight
difference in the offset level for odd and even pixels, called
“pixel-to-pixel offset” (see Specifications). T he pixel-to-pixel
offset is an output referred specification, because the black level
correction is done using the output of the PGA.
PGA
ADC
IN
CLPOB
NEG REF
CONTROL
CDS1
RPGA2
INT2
CDS2
RPGA1
INT1
Figure 19.
Input Bias Level Clamping
T he buffered CCD output is connected to the AD9802 through
an external coupling capacitor. T he dc bias point for this cou-
pling capacitor is established during the clamping (CLPDM =
LOW) period using the “dummy clamp” loop shown in Figure
20. When closed around the CDS, this loop establishes the
desired dc bias point on the coupling capacitor.
BLACK
LEVEL CLP
CCD
INPUT
CLAMP
CLPDM
TO ADC
PGA
CDS
Figure 20.
Input Blanking
In some applications, the AD9802’s input may be exposed to
large signals from the CCD. T hese signals can be very large,
relative to the AD9802’s input range, and could thus saturate
on-chip circuit blocks. Recovery time from such saturation
conditions could be substantial.
T o avoid problems associated with processing these transients,
the AD9802 includes an input blanking function. When active
(PBLK = LOW) this function stops the CDS operation and
allows the user to disconnect the CDS inputs from the CCD
buffer.
If the input voltage exceeds the supply rail by more than 0.3V,
then protection diodes will be turned on, increasing current flow
into the AD9802 (see Equivalent Input Circuits). Such voltage
levels should be externally clamped to prevent device damage or
reliability degradation.
10-Bit Analog-to-Digital Converter (ADC)
T he ADC employs a multibit pipelined architecture that is
well suited for high throughput rates while being both area and
power efficient. T he multistep pipeline presents a low input
capacitance resulting in lower on-chip drive requirements. A
fully differential implementation was used to overcome head-
room constraints of the single +3 V power supply.
Direct ADC Input
T he analog processing circuitry may be bypassed in the
AD 9802. When AD C MOD E (Pin 41) is taken high, the
ADCIN pin provides a direct input to the SHA. T his feature
allows digitization of signals that do not require CDS and
gain adjustment. T he PGA output is disconnected from the
SHA when ADCMODE is taken high.
Differential Reference
T he AD9802 includes a 0.5 V reference based on a differential,
continuous-time bandgap cell. Use of an external bypass capaci-
tor reduces the reference drive requirements, thus lowering the
power dissipation. T he differential architecture was chosen for
its ability to reject supply and substrate noise. Recommended
decoupling shown in Figure 21.
VRT
REF
VRB
1
m
F
0.1
m
F
0.1
m
F
Figure 21.
Internal T iming
T he AD9802’s on-chip timing circuitry generates all clocks
necessary for operation of the CDS and ADC blocks. T he user
needs only to synchronize the SHP and SHD clocks with the
CCD waveform, as all other timing is handled internally. T he
ADCCLK signal is used to strobe the output data, and can be
adjusted to accommodate desired timing.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9802 | .50" x 50 Black/Clear 240 Industrial Label Supply RoHS Compliant: NA |
| AD9803 | CCD And Video Signal Processor For Electronic Cameras(電子照相機(jī)的CCD信號(hào)和視頻信號(hào)處理器) |
| AD9805 | Complete 12-Bit/10-Bit 6 MSPS CCD/CIS Signal Processors |
| AD9805JS | Complete 12-Bit/10-Bit 6 MSPS CCD/CIS Signal Processors |
| AD9807 | Complete 12-Bit/10-Bit 6 MSPS CCD/CIS Signal Processors |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9802JSTRL | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| AD9803 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CCD Signal Processor For Electronic Cameras |
| AD9803JST | 制造商:Rochester Electronics LLC 功能描述: |
| AD9803JST-28 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9803JSTRL-28 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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