TMIN to T
參數(shù)資料
型號： AD9788-DPG2-EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 34/64頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD9788
設(shè)計資源： Powering the AD9788 Using ADP2105 for Increased Efficiency (CN0141)
標(biāo)準(zhǔn)包裝： 1
系列： *
DAC 的數(shù)量： 2
位數(shù)： 16
采樣率（每秒）： 800M
數(shù)據(jù)接口： 串行
設(shè)置時間： 22ms
DAC 型： 電流
工作溫度： -40°C ~ 85°C
已供物品： *
已用 IC / 零件： AD9788
AD9785/AD9787/AD9788
Rev. A | Page 4 of 64
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless
otherwise noted.
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
CMOS INPUT LOGIC LEVEL
Input VIN Logic High
2.0
V
Input VIN Logic Low
0.8
V
LVDS INPUT (SYNC_I+, SYNC_I)
SYNC_I+ = V1A, SYNC_I = V1B
Input Voltage Range, VIA or VIB
825
1575
mV
Input Differential Threshold, VIDTH
–100
+100
mV
Input Differential Hysteresis, VIDTHH VIDTHL
20
mV
Receiver Differential Input Impedance, RIN
80
120
Ω
LVDS Input Rate (fSYNC_I = fDATA)
30
MHz
Setup Time, SYNC_I to DAC Clock
0.45
ns
Hold Time, SYNC _I to DAC Clock
0.25
ns
LVDS DRIVER OUTPUTS (SYNC_O+, SYNC_O)
SYNC_O+ = VOA, SYNC_O = VOB, 100 Ω termination
Output Voltage High, VOA or VOB
825
1575
mV
Output Voltage Low, VOA or VOB
1025
mV
Output Differential Voltage, |VOD|
150
200
250
mV
Output Offset Voltage, VOS
1150
1250
mV
Output Impedance, Single-Ended, RO
80
100
120
Ω
DAC CLOCK INPUT (REFCLK+, REFCLK–)
Differential Peak-to-Peak Voltage
400
800
1600
mV
Common-Mode Voltage
300
400
500
mV
Maximum Clock Rate
DVDD18 = 1.8 V ± 5%
800
MHz
DVDD18 = 1.9 V ± 5%
900
MHz
REFCLK Frequency Range, PLL Enabled
30
250
MHz
MAXIMUM INPUT DATA RATE
1× Interpolation
250
MSPS
2× Interpolation
250
MSPS
4× Interpolation
DVDD18 = 1.8 V ± 5%
200
MSPS
DVDD18 = 1.9 V ± 5%
225
MSPS
8× Interpolation
DVDD18 = 1.8 V ±5%
100
MSPS
DVDD18 = 1.9 V ± 5%
112.5
MSPS
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK)
40
MHz
Minimum Pulse Width High
12.5
ns
Minimum Pulse Width Low
12.5
ns
Setup Time, SPI_SDIO to SCLK
2.8
ns
Hold Time, SPI_SDIO to SCLK
0.0
ns
Setup Time, SPI_CSB to SCLK
3.0
ns
Data Valid, SPI_SDO to SCLK
10.0
ns
INPUT DATA
All modes, 40°C to +85°C1
Setup Time, Input Data to DATACLK
460
ns
Hold Time, Input Data to DATACLK
1.5
ns
Setup Time, Input Data to REFCLK
0.25
ns
Hold Time, Input Data to REFCLK
2.4
ns
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