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參數(shù)資料
| 型號： | AD9787BSVZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 800MSPS 100TQFP |
| 產品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1,000 |
| 系列： | TxDAC® |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 450mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應商設備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電流，單極；4 電流，雙極 |
| 采樣率（每秒）： | 800M |
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AD9785/AD9787/AD9788
Rev. A | Page 20 of 64
TERMINOLOGY
Integral Nonlinearity (INL)
INL is defined as the maximum deviation of the actual analog
output from the ideal output, determined by a straight line
drawn from zero scale to full scale.
Differential Nonlinearity (DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when the
inputs are all 0s. For IOUTB, 0 mA output is expected when all
inputs are set to 1.
Gain Error
The difference between the actual and ideal output span is
called gain error. The actual span is determined by the differ-
ence between the output when all inputs are set to 1 and the
output when all inputs are set to 0.
Output Compliance Range
The output compliance range is the range of allowable voltage
at the output of a current output DAC. Operation beyond the
maximum compliance limits can cause either output stage
saturation or breakdown, resulting in nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (25°C) value to the value at either TMIN or TMAX. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree Celsius. For reference drift, the drift is
reported in ppm per degree Celsius.
Power Supply Rejection (PSR)
PSR is the maximum change in the full-scale output as the
supplies are varied from minimum to maximum specified
voltages.
Settling Time
Settling time is the time required for the output to reach and
remain within a specified error band around its final value,
measured from the start of the output transition.
Spurious-Free Dynamic Range (SFDR)
Spurious-free dynamic range is the difference, in decibels,
between the peak amplitude of the output signal and the peak
amplitude of the largest spurious signal in a given frequency
band from the signal. For out-of-band SFDR, the frequency
band is 0 to one half the DAC sample rate. For in-band SFDR,
the frequency band is 0 to one half the input data rate.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured fundamental. It is
expressed as a percentage or in decibels.
Noise Spectral Density (NSD)
NSD is the noise power at the analog output measured in a 1 Hz
bandwidth.
Interpolation Filter
If the digital inputs to the DAC are sampled at a multiple rate of
fDATA (interpolation rate), a digital filter can be constructed that
has a sharp transition band near fDATA/2. Images that typically
appear around fDAC (output data rate) can be greatly suppressed.
Adjacent Channel Leakage Ratio (ACLR)
ACLR is the ratio in dBc between the measured power within a
channel relative to its adjacent channel.
Complex Image Rejection
In a traditional two-part upconversion, two images are created
around the second intermediate frequency (IF). These images
have the effect of wasting transmitter power and system band-
width. By placing the real part of a second complex modulator
in series with the first complex modulator, either the upper or
lower frequency image near the second IF can be rejected.
Sinc
Sinc is shorthand for the mathematical function
sinc(x) = sin(x)/x
This function is a useful tool for digital signal processing. The
normalized sinc function is used here and is defined as follows:
sinc(x) = sin(π × x)/(π × x)
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| AD9787-DPG2-EBZ | 功能描述:BOARD EVALUATION FOR AD9787 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉換器 (DAC) 系列:* 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
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| AD9788BSVZ | 功能描述:IC DAC 16BIT 800MSPS 100TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:TxDAC® 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 設置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應商設備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產品目錄頁面:1398 (CN2011-ZH PDF) |
| AD9788BSVZRL | 功能描述:IC DAC 16BIT 800MSPS 100TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:TxDAC® 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1,000 系列:- 設置時間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
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