參數(shù)資料
型號(hào)： AD9786BSVRL
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： 16-Bit, 200 MSPS/500 MSPS TxDAC+ with 2】/4】/8】 Interpolation and Signal Processing
中文描述： PARALLEL, WORD INPUT LOADING, 16-BIT DAC, PQFP80
封裝： PLASTIC, MS-026-ADD, TQFP-80
文件頁(yè)數(shù)： 22/60頁(yè)
文件大?。?/td> 1497K
代理商： AD9786BSVRL
AD9786
Table 14.
Rev. 0 | Page 22 of 60
DATA(02)
DATAFMT
Bit
7
Direction
I
Default
0
Description
0: Twos complement data format
1: Unsigned binary input data format
0: I and Q input data onto ports one and two, respectively
1: I and Q input data interleaved onto port one
0: DATACLK pin 12 mA drive strength
1: DATACLK pin 24 mA drive strength
0: Input data latched on DATACLK rising edge
1: Input data latched on DATACLK falling edge
0: DATACLK pin inputs channel data rate or modulator synchronizer clock
1: DATACLK pin outputs channel data rate or modulator synchronizer clock
0: With DATACLK pin as input, DATACLK clock recovery off
1: With DATACLK pin as input, DATACLK clock recovery on
0: In one port mode, IQSEL = 1 latches data into I channel, IQSEL = 0 latches data
into Q channel
1: In one port mode, IQSEL = 0 latches data into I channel, IQSEL = 1 latches data
into Q channel
0: Gray decoder off
1: Gray decoder on
ONEPORT
6
I
0
DCLKSTR
5
I
0
DCLKPOL
4
I
0
DCLKEXT
3
I
0
DCLKCRC
2
I
0
IQPOL
1
I
0
GRAYDIN
0
I
0
Table 15.
MODULATE(03)
CHANNEL
Bit
7
Direction
I
Default
0
Description
MODDUAL
03h [5]
0
0
1
1
1: With MODDUAL on, Hilbert transform on
0: Modulator uses a single channel
1: Modulator uses both I and Q channels
0: With MODDUAL on, lower sideband rejected
1: With MODDUAL on, upper sideband rejected
00: No modulation
01: f
S
/2 modulation
10: f
S
/4 modulation
11: f
S
/8 modulation
CHANNEL
03h[7]
0
1
0
1
I channel processing routed to DAC
Q channel processing routed to DAC
Modulator real output routed to DAC
Modulator imaginary output routed to DAC
HILBERT
MODDUAL
6
5
I
I
0
0
SIDEBAND
4
I
0
MOD[1:0]
[3:2]
I
00
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