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參數(shù)資料
| 型號(hào)： | AD9783-DPG2-EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9783 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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Data Sheet
AD9780/AD9781/AD9783
Rev. B | Page 27 of 32
06936-
076
CH1 100mV
A CH1
58mV
1
125ps/DIV 2.12ns
20GSPS IT 2.5ps/PT
V1: 296mV
V2: –228mV
ΔV: –524mV
Figure 58. Eye Diagram of Data Source Used in Building the 500 MHz Timing
Data Array of Table 14
Over temperature, the valid sampling window shifts. Therefore,
when attempting operation of the device over 500 MHz, the
timing must be optimized again whenever the device undergoes
a temperature change of more than 20oC. Another consideration
in the timing of the digital data port is the propagation delay
variation from the clock output (DCOP/DCON) to the clock
input. If this varies significantly over time (more than 25% of
SET or HLD) due to temperature changes or other effects,
repeat this timing calibration procedure.
At sample rates of ≤400 MSPS, the interface timing margin is
sufficient to allow for a simplified procedure. In this case, the
SEEK bit can be recorded as SMP is swept through the range
from 0 to 31. The center of the first valid sampling window can
then be chosen as the optimal value of SMP. Using the 400 MHz
case from Table 14 as an example, the first valid sampling
window occurs for SMP values of 7 to 13. The center of this
window is 10, so 10 can be used as the optimal SMP value.
BIST OPERATION
The BIST feature in the AD9780/AD9781/AD9783 is a simple
type adder and is a user synchronizable BIST feature. In
Register 0x1A, write 0x20 then 0x00 to clear the BIST registers
while writing zeros to the data bits for at least eight clock cycles
to propagate to the BIST signature module. Then enable BIST
by writing 0x80 to Register 0x1A. Next, begin writing a known
set of vectors to the data inputs. Proceed by writing zeros into
the bits after the vectors while the BIST read is being performed.
Perform a BIST read by writing 0xC0 to Register 0x1A to
receive the unique sum of rising edge data in Register 0x1B
and Register 0x1C and a unique sum of falling edge data in
Register 0x1D and Register 0x1E. These register contents
should always give the same values for the same vectors
each time they are sent.
DRIVING THE CLK INPUT
The CLK input requires a low jitter differential drive signal. It is
a PMOS input differential pair powered from the 1.8 V supply;
therefore, it is important to maintain the specified 400 mV
input common-mode voltage. Each input pin can safely swing
from 200 mV p-p to 1 V p-p about the 400 mV common-mode
voltage. CLK can be driven by an offset ac-coupled signal, as
shown in Figure 59.
P_IN
CLKP
50
0.1F
N_IN
CLKN
VCM = 400mV
06936-
056
Figure 59. DAC CLK Drive Circuit
If a clean sine clock is available, it can be transformer-coupled
to CLKP and CLKN as shown in Figure 60. Use of a CMOS or
TTL clock is also acceptable for lower sample rates. It can then
be ac-coupled, as described in this section. Alternatively, it can
be transformer-coupled and clamped, as shown in Figure 60.
50
TTL OR CMOS
CLK INPUT
CLKP
CLKN
VCM = 400mV
BAV99ZXCT
HIGH SPEED
DUAL DIODE
0.1F
06936-
057
Figure 60. TTL or CMOS DAC CLK Drive Circuit
A simple bias network for generating the 400 mV common-
mode voltage is shown in Figure 61. It is important to use
CVDD18 and CGND for the clock bias circuit. Any noise or
other signal coupled onto the clock is multiplied by the DAC
digital input signal and can degrade the DAC’s performance.
0.1F
1nF
VCM = 400mV
CVDD18
CGND
1k
287
1nF
06936-
058
Figure 61. DAC CLK VCM Generator Circuit
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