參數(shù)資料
型號(hào)： AD9774ASZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 2/24頁(yè)
文件大?。?/td> 0K
描述： IC DAC 14BIT 32MSPS 44-MQFP
產(chǎn)品培訓(xùn)模塊： DAC Architectures
產(chǎn)品變化通告： Product Discontinuance 27/Oct/2011
標(biāo)準(zhǔn)包裝： 1
系列： TxDAC+®
設(shè)置時(shí)間： 35ns
位數(shù)： 14
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 1.13W
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 44-QFP
供應(yīng)商設(shè)備封裝： 44-MQFP（10x10）
包裝： 托盤(pán)
輸出數(shù)目和類(lèi)型： 2 電流，單極；2 電流，雙極
采樣率（每秒）： 32M
AD9774
–10–
REV. B
FUNCTIONAL DESCRIPTION
Figure 22 shows a simplified block diagram of the AD9774. The
AD9774 is a complete, 4
× oversampling, 14-bit DAC that in-
cludes two cascaded 2
× interpolation filters, a phase-locked loop
(PLL) clock multiplier, and a 1.20 Volt bandgap voltage refer-
ence. The 14-bit DAC provides two complementary current
outputs whose full-scale current is determined by an external
resistor. Input data that is latched into the edge-triggered input
latches is first interpolated by a factor of four by the interpolation
filters before updating the 14-bit DAC. A PLL clock multiplier
produces the necessary internally synchronized 1
×, 2× and 4×
clocks from an external reference. The AD9774 can support
input data rates as high as 32 MSPS, corresponding to a DAC
update rate of 128 MSPS.
The analog and digital sections of the AD9774 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
over a 2.7 V to 5.5 V range. A separate supply input (i.e.,
PLLVDD) having a similar operating range is also provided for
the PLL clock multiplier. To maintain optimum noise and dis-
tortion performance, PLLVDD should be maintained at the
same voltage level as DVDD.
VCO
IN/EXT
PLL
DIVIDE
PLLCOM
PLL CLOCK
MULTIPLIER
REFIO
SNOOZE
IOUTA
FSADJ
AD9774
SLEEP
DCOM DVDD ICOMP ACOM AVDD
+1.2V REFERENCE
AND CONTROL AMP
PLL
ENABLE
PLLLOCK
CLK4 IN
PLLVDD
LPF
IOUTB
EDGE
TRIGGERED
LATCHES
14
14-BIT
DAC
DATA
INPUTS
(DB13–DB0)
2
1
2
4
14
CLK IN/OUT
REFCOMP REFLO
Figure 22. Functional Block Diagram
Preceding the 14-bit DAC are two cascaded
2× digital interpola-
tion filter stages based on a 55- and 23-tap halfband symmetric
FIR topology. Edge triggered latches are used to latch the input
data on the rising edge of CLK IN/OUT. The composite fre-
quency and impulse response of both filters are shown in Fig-
ures 2a and 2b. Table I and Table II list the idealized filter
coefficients for each of the filter stages. The interpolation filters
essentially multiply the input data rate to the DAC by a factor of
four relative to its original input data rate while simultaneously
reducing the magnitude of the images associated with the origi-
nal input data rate.
The benefits of an interpolation filter are clearly seen in Figure
23, which shows an example of the frequency and time domain
representation of a discrete time sine wave signal before and
after it is applied to a digital interpolation filter. Images of the
sine wave signal appear around multiples of the DAC’s input
data rate as predicted by sampling theory. These undesirable
images will also appear at the output of a reconstruction DAC,
although modified by the DAC’s sin(x)/(x) roll-off response.
In many bandlimited applications, these images must be sup-
pressed by an analog filter following the DAC. The complexity
of this analog filter is typically determined by the proximity of
the desired fundamental to the first image and the required
amount of image suppression. Adding to the complexity of this
analog filter may be the requirement of compensating for the
DAC’s sin(x)/x response.
Referring to Figure 23, the “new” first image associated with the
DAC’s higher data rate after interpolation is “pushed” out fur-
ther relative to the input signal. The “old” first image associated
with the lower DAC data rate before interpolation is suppressed
by the digital filter. As a result, the transition band for the ana-
log reconstruction filter is increased, thus reducing the complex-
ity of the analog filter. Furthermore, the sin(x)/x roll-off over the
effective passband (i.e., dc to fCLOCK/2) is significantly reduced.
The AD9774 includes a PLL clock multiplier that produces the
necessary internally synchronized 1
×, 2× and 4× clocks for the
edge triggered latches, interpolation filters and DACs. The
PLL clock multiplier typically accepts an input data clock,
CLK IN/OUT, as its reference source. Alternatively, it can also
be configured using an external 4
× clock via CLK4×IN. The
PLLDIVIDE, VCO IN/EXT, PLLENABLE, and PLLLOCK
are control inputs/outputs used in the PLL clock generator.
Refer to the PLL CLOCK MULTIPLIER OPERATION sec-
tion for a detailed discussion on its operation.
The digital section of the AD9774 also includes several other
control inputs and outputs. The SLEEP and SNOOZE inputs
provide different power-saving modes as discussed in the
SLEEP and SNOOZE section.
FUNDAMENTAL
4fCLOCK
2fCLOCK
FREQUENCY DOMAIN
4fCLOCK
DACs
"SINX"
X
2fCLOCK
1
4
f
CLOCK
FUNDAMENTAL
DIGITAL
FILTER
SUPPRESSED
"OLD"
1ST IMAGE
"NEW"
1ST IMAGE
4fCLOCK
2fCLOCK
1
f
CLOCK
TIME DOMAIN
4x INTERPOLATION FILTER
INPUT DATA LATCH
DAC
4 fCLOCK
fCLOCK
4x
1ST IMAGE
Figure 23. Time and Frequency Domain Example of Digital Interpolation Filter
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AD9774ASZRL 功能描述:IC DAC 14BIT 32MSPS 44MQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 標(biāo)準(zhǔn)包裝:2,400 系列:- 設(shè)置時(shí)間:- 位數(shù):18 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:3 電壓電源:模擬和數(shù)字 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:36-TFBGA 供應(yīng)商設(shè)備封裝:36-TFBGA 包裝:帶卷 (TR) 輸出數(shù)目和類(lèi)型:* 采樣率（每秒）:*
AD9774EB 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:14-Bit, 32 MSPS TxDAC⑩ with 4x Interpolation Filters
AD9774-EB 制造商:Analog Devices 功能描述:
AD9774-EBZ 制造商:Analog Devices 功能描述:14-BIT 32 MSPS TXDAC W/4X INTERPOLATION - Bulk
AD9775 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:14-Bit, 160 MSPS 2X/4X/8X Interpolating Dual TxDAC+ D/A Converter
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