參數(shù)資料
型號: AD9774AS
廠商: ANALOG DEVICES INC
元件分類: DAC
英文描述: 14-Bit, 32 MSPS TxDAC⑩ with 4x Interpolation Filters
中文描述: PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 14-BIT DAC, PQFP44
封裝: METRIC, QFP-44
文件頁數(shù): 3/24頁
文件大?。?/td> 313K
代理商: AD9774AS
–3–
REV. B
AD9774
DYNAMIC SPECIFICATIONS
Parameter
Min
Typ
Max
Units
DYNAMIC PERFORMANCE
Maximum Output Update Rate w/DVDD = 5 V
Maximum Output Update Rate
w/DVDD = 3 V
Output Settling Time (t
ST
) (to 0.025%)
Output Propagation Delay (t
PD
)
Glitch Impulse
Output Rise Time (10% to 90%)
1
Output Fall Time (10% to 90%)
1
Output Noise (I
OUTFS
= 20 mA)
128
100
MSPS
MSPS
ns
Clocks
1
pV-s
ns
ns
pA/
Hz
2
128
35
55
5
2.5
2.5
50
AC LINEARITY TO NYQUIST
Spurious-Free Dynamic Range (SFDR) to Nyquist
f
CLOCK
= 25 MSPS; f
OUT
= 1.01 MHz
0 dBFS Output
–6 dBFS Output
–12 dBFS Output
–18 dBFS Output
f
CLOCK
= 32 MSPS; f
OUT
= 1.01 MHz
f
CLOCK
= 32 MSPS; f
OUT
= 5.01 MHz
f
CLOCK
= 32 MSPS; f
OUT
= 10.01 MHz
f
CLOCK
= 32 MSPS; f
OUT
= 13.01 MHz
Total Harmonic Distortion (THD)
f
CLOCK
= 25 MSPS; f
OUT
= 1.01 MHz; 0 dBFS
Signal-to-Noise Ratio (SNR)
f
CLOCK
= 25 MSPS; f
OUT
= 1.01 MHz; 0 dBFS
NOTES
1
Propagation delay is delay from data input to DAC update.
2
Measured single-ended into 50
load.
Specifications subject to change without notice.
79
86
75
75
78
77
79
78
dB
dB
dB
dB
dB
dB
dB
dB
–75
dB
76
dB
(T
MIN
to T
MAX
, AVDD = +5 V, PLLVDD = +5 V, DVDD = +5 V, I
OUTFS
= 20 mA, Differential Transformer
Coupled Output, 50
V
Doubly Terminated, unless otherwise noted)
DIGITAL SPECIFICATIONS
Parameter
Min
Typ
Max
Units
DIGITAL INPUTS
Logic “1” Voltage @ DVDD = +5 V
Logic “1” Voltage @ DVDD = +3 V
Logic “0” Voltage @ DVDD = +5 V
Logic “0” Voltage @ DVDD = +3 V
Logic “1” Current
Logic “0” Current
Input Capacitance
Input Setup Time (t
S
)
Input Hold Time (t
H
)
Latch Pulsewidth (t
LPW
)
3.5
2.1
5
3
0
0
V
V
V
V
μ
A
μ
A
pF
ns
ns
ns
1.3
0.9
+10
+10
–10
–10
5
2.5
1.5
4
(T
MIN
to T
MAX
, AVDD = +5 V, PLLVDD = +5 V, DVDD = +5 V, I
OUTFS
= 20 mA unless otherwise noted)
0.025%
0.025%
t
S
t
H
t
LPW
t
PD
t
ST
DB0–DB11
CLOCK
IOUTA
OR
IOUTB
Figure 1. Timing Diagram
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