參數(shù)資料
型號(hào)： AD9767AST
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： 14-Bit, 125 MSPS Dual TxDAC+ D/A Converter
中文描述： DUAL, PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 14-BIT DAC, PQFP48
封裝： MS-026BBC, LQFP-48
文件頁(yè)數(shù)： 9/27頁(yè)
文件大?。?/td> 469K
代理商： AD9767AST
REV. B
AD9767
–9–
FUNCTIONAL DESCRIPTION
Figure 20 shows a simplified block diagram of the AD9767.
The AD9767 consists of two DACs, each with its own indepen-
dent digital control logic and full-scale output current control.
Each DAC contains a PMOS current source array capable of
providing up to 20 mA of full-scale current (I
OUTFS
). The array
is divided into 31 equal currents that make up the five most
significant bits (MSBs). The next four bits, or middle bits,
consist of 15 equal current sources whose value is 1/16th of an
MSB current source. The remaining LSB is a binary weighted
fraction of the middle bit current sources. Implementing the
middle and lower bits with current sources, instead of an R-2R
ladder, enhances the dynamic performance for multitone or low
amplitude signals and helps maintain the DAC’s high output
impedance (i.e., >100 k
).
All of these current sources are switched to one or the other of
the two output nodes (i.e., I
OUTA
or I
OUTB
) via PMOS differen-
tial current switches. The switches are based on a new architec-
ture that drastically improves distortion performance. This new
switch architecture reduces various timing errors and provides
matching complementary drive signals to the inputs of the dif-
ferential current switches.
The analog and digital sections of the AD9767 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 3 V to 5.5 V range. The digital section,
which is capable of operating up to a 125 MSPS clock rate,
consists of edge-triggered latches and segment decoding logic
circuitry. The analog section includes the PMOS current sources,
the associated differential switches, a 1.20 V bandgap voltage
reference and two reference control amplifiers.
The full-scale output current of each DAC is regulated by sepa-
rate reference control amplifiers and can be set from 2 mA to
20 mA via an external resistor, R
SET
, connected to the Full
Scale Adjust (FSADJ) pin. The external resistor, in combination
with both the reference control amplifier and voltage reference
V
REFIO
, sets the reference current I
REF
, which is replicated to the
segmented current sources with the proper scaling factor. The
full-scale current, I
OUTFS
, is 32
×
I
REF
.
I
OUTA2
I
OUTB2
5V
I
OUTA1
I
OUTB1
SEGMENTED
SWITCHES FOR
DAC1
LSB
SWITCH
SEGMENTED
SWITCHES FOR
DAC2
LSB
SWITCH
DAC 2
LATCH
DAC 1
LATCH
CLK
DIVIDER
PMOS
CURRENT
SOURCE
ARRAY
PMOS
CURRENT
SOURCE
ARRAY
CLK1/IQCLK
CLK2/IQRESET
AVDD
FSADJ1
REFIO
FSADJ2
1.2V REF
MODE
DVDD
DCOM
MULTIPLEXING LOGIC
5V
WRT1/
IQWRT
GAINCTRL
0.1 F
R
SET
2
2k
R
SET
1
2k
SLEEP
ACOM
DIGITAL DATA INPUTS
AD9767
I
REF
1
I
REF
2
R
L
2B
50
R
L
2A
50
V
OUT
2B
V
OUT
2A
R
L
1B
50
R
L
1A
50
V
OUT
1B
V
OUT
1A
V
DIFF
= V
OUT
A
–
V
OUT
B
WRT2/
IQSEL
DB0
–
DB13
DB0
–
DB13
CHANNEL 2 LATCH
CHANNEL 1 LATCH
Figure 20. Simplified Block Diagram
REFERENCE OPERATION
The AD9767 contains an internal 1.20 V bandgap reference.
This can easily be overridden by an external reference with no
effect on performance. REFIO serves as either an
input
or
out-
put
, depending on whether the internal or an external reference
is used. To use the internal reference, simply decouple the
REFIO pin to ACOM with a 0.1
μ
F capacitor. The internal
reference voltage will be present at REFIO. If the voltage at
REFIO is to be used elsewhere in the circuit, an external buffer
amplifier with an input bias current of less than 100 nA should
be used. An example of the use of the internal reference is
shown in Figure 21.
+1.2V
REF
AVDD
GAINCTRL
CURRENT
SOURCE
ARRAY
REFIO
FSADJ
2k
0.1 F
ADDITIONAL
EXTERNAL
LOAD
OPTIONAL
EXTERNAL
REFERENCE
BUFFER
AD9767
REFERENCE
SECTION
I
REF
ACOM
Figure 21. Internal Reference Configuration
An external reference can be applied to REFIO as shown in
Figure 22. The external reference may provide either a fixed
reference voltage to enhance accuracy and drift performance or
a varying reference voltage for gain control. Note that the 0.1
μ
F
compensation capacitor is not required since the internal refer-
ence is overridden, and the relatively high input impedance of
REFIO minimizes any loading of the external reference.
+1.2V
REF
AVDD
GAINCTRL
CURRENT
SOURCE
ARRAY
REFIO
FSADJ
2k
AD9767
REFERENCE
SECTION
I
REF
ACOM
AVDD
EXTERNAL
REFERENCE
Figure 22. External Reference Configuration
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