參數(shù)資料
型號(hào)： AD9767AST
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： 14-Bit, 125 MSPS Dual TxDAC+ D/A Converter
中文描述： DUAL, PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 14-BIT DAC, PQFP48
封裝： MS-026BBC, LQFP-48
文件頁(yè)數(shù)： 6/27頁(yè)
文件大?。?/td> 469K
代理商： AD9767AST
REV. B
AD9767
–6–
DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input
code.
Monotonicity
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For I
OUTA
, 0 mA output is expected when the
inputs are all 0s. For I
OUTB
, 0 mA output is expected when all
inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown resulting in
nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (+25
°
C) value to the value at either T
MIN
or T
MAX
. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree C. For reference drift, the drift is
reported in ppm per degree C (ppm/
°
C).
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Total Harmonic Distortion
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal. It is
expressed as a percentage or in decibels (dB).
I
OUTA2
I
OUTB2
5V
50
I
OUTA1
I
OUTB1
SEGMENTED
SWITCHES FOR
DAC1
LSB
SWITCH
SEGMENTED
SWITCHES FOR
DAC2
LSB
SWITCH
DAC 2
LATCH
DAC 1
LATCH
CLK
DIVIDER
PMOS
CURRENT
SOURCE
ARRAY
PMOS
CURRENT
SOURCE
ARRAY
CLK1/IQCLK
CLK2/IQRESET
AVDD
FSADJ1
REFIO
FSADJ2
1.2V REF
MODE
DVDD
MULTIPLEXING LOGIC
5V
WRT2/
IQSEL
WRT1/
IQWRT
GAINCTRL
0.1 F
R
SET
2
R
SET
1
50
50
MINI
CIRCUITS
T1-1T
TO HP3589A
SPECTRUM/
NETWORK
ANALYZER
DCOM
SLEEP
ACOM
DB0
–
DB13
DB0
–
DB13
DIGITAL
DATA
LECROY 9210
PULSE
GENERATOR
*RETIMED CLOCK OUTPUT
DVDD
DCOM
AD9767
*AWG2021 CLOCK RETIMED SUCH THAT
DIGITAL DATA TRANSITIONS ON FALLING
EDGE OF 50% DUTY CYCLE CLOCK
CHANNEL 2 LATCH
CHANNEL 1 LATCH
TEKTRONIX
AWG-2021
w/OPTION 4
Figure 2. Basic AC Characterization Test Setup for AD9767, Testing Port 1 in Dual Port Mode, Using Independent
GAINCTRL Resistors on FSADJ1 and FSADJ2
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