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參數(shù)資料
| 型號： | AD9763 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 10-Bit, 125 MSPS Dual TxDAC+ D/A Converter |
| 中文描述： | 10位，125 MSPS的TxDAC系列雙D / A轉(zhuǎn)換 |
| 文件頁數(shù)： | 15/28頁 |
| 文件大?。?/td> | 460K |
| 代理商： | AD9763 |
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REV. B
AD9763
–
15
–
The differential circuit shown in Figure 35 provides the neces-
sary level-shifting required in a single supply system. In this
case AVDD, which is the positive analog supply for both the
AD9763 and the op amp, is also used to level-shift the differ-
ential output of the AD9763 to midsupply (i.e., AVDD/2). The
AD8055 is a suitable op amp for this application.
AD9763
I
OUTA
I
OUTB
C
OPT
500
225
225
500
25
25
AD8055
1k
AVDD
Figure 35. Single Supply DC Differential Coupled Circuit
SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT
Figure 36 shows the AD9763 configured to provide a unipolar
output range of approximately 0 V to +0.5 V for a doubly ter-
minated 50
cable since the nominal full-scale current, I
OUTFS
,
of 20 mA flows through the equivalent R
LOAD
of 25
. In this
case, R
LOAD
represents the equivalent load resistance seen by
I
OUTA
or I
OUTB
. The unused output (I
OUTA
or I
OUTB
) can be
connected to ACOM directly or via a matching R
LOAD
. Differ-
ent values of I
OUTFS
and R
LOAD
can be selected as long as the
positive compliance range is adhered to. One additional con-
sideration in this mode is the integral nonlinearity (INL) as
discussed in the Analog Output section of this data sheet. For
optimum INL performance, the single-ended, buffered voltage
output configuration is suggested.
AD9763
I
OUTA
I
OUTB
50
25
50
V
OUTA
= 0 TO +0.5V
I
OUTFS
= 20mA
Figure 36. 0 V to 0.5 V Unbuffered Voltage Output
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT
CONFIGURATION
Figure 37 shows a buffered single-ended output configura-
tion in which the op amp U1 performs an I-V conversion on
the AD9763 output current. U1 maintains I
OUTA
(or I
OUTB
) at a
virtual ground, thus minimizing the nonlinear output imped-
ance effect on the DAC’s INL performance as discussed in
the Analog Output section. Although this single-ended configu-
ration typically provides the best dc linearity performance, its ac
distortion performance at higher DAC update rates may be
limited by U1’s slewing capabilities. U1 provides a negative
unipolar output voltage and its full-scale output voltage is sim-
ply the product of R
FB
and I
OUTFS
. The full-scale output should
be set within U1’s voltage output swing capabilities by scaling
I
OUTFS
and/or R
FB
. An improvement in ac distortion perfor-
mance may result with a reduced I
OUTFS
since the signal current
U1 will be required to sink will be subsequently reduced.
AD9763
I
OUTA
I
OUTB
C
OPT
200
U1
V
OUT
= I
OUTFS
R
FB
I
OUTFS
= 10mA
R
FB
200
Figure 37. Unipolar Buffered Voltage Output
POWER AND GROUNDING CONSIDERATIONS, POWER
SUPPLY REJECTION
Many applications seek high speed and high performance under
less than ideal operating conditions. In these application cir-
cuits, the implementation and construction of the printed circuit
board is as important as the circuit design. Proper RF tech-
niques must be used for device selection, placement and rout-
ing, as well as power supply bypassing and grounding to ensure
optimum performance. Figures 44 to 51 illustrate the recom-
mended printed circuit board ground, power and signal plane
layouts which are implemented on the AD9763 evaluation board.
One factor that can measurably affect system performance is the
ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution.
This is referred to as the Power Supply Rejection Ratio. For dc
variations of the power supply, the resulting performance of the
DAC directly corresponds to a gain error associated with the
DAC’s full-scale current, I
OUTFS
. AC noise on the dc supplies is
common in applications where the power distribution is gener-
ated by a switching power supply. Typically, switching power
supply noise will occur over the spectrum from tens of kHz to
several MHz. The PSRR vs. frequency of the AD9763 AVDD
supply over this frequency range is shown in Figure 38.
FREQUENCY
–
MHz
P
–
90
70
0.20
85
80
75
0.30
0.40
0.50
0.60
0.70
0.80
0.90
1.00
1.10
Figure 38. Power Supply Rejection Ratio of AD9763
Note that the units in Figure 38 are given in units of (amps out/
volts in). Noise on the analog power supply has the effect of
modulating the internal current sources, and therefore the out-
put current. The voltage noise on AVDD, therefore, will be
added in a nonlinear manner to the desired I
OUT
. PSRR is very
code-dependent thus producing mixing effects which can modu-
late low frequency power supply noise to higher frequencies.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9763-EB | 10-Bit, 125 MSPS Dual TxDAC+ D/A Converter |
| AD9763AST | 10-Bit, 125 MSPS Dual TxDAC+ D/A Converter |
| AD9764 | 14-Bit, 125 MSPS TxDAC D/A Converter |
| AD9764-EB | 14-Bit, 125 MSPS TxDAC D/A Converter |
| AD9764AR | 14-Bit, 125 MSPS TxDAC D/A Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9763_11 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-/12-/14-Bit, 125 MSPS Dual TxDAC Digital-to-Analog Converters |
| AD9763AST | 制造商:Analog Devices 功能描述:DAC 2-CH Segment 10-bit 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:10 BIT, 125 MSPS DUAL TXDAC+ - Tape and Reel 制造商:Analog Devices 功能描述:IC 10-BIT DAC |
| AD9763ASTRL | 制造商:Analog Devices 功能描述:DAC 2-CH Segment 10-bit 48-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:10 BIT, 125 MSPS DUAL TXDAC+ - Tape and Reel |
| AD9763ASTZ | 功能描述:IC DAC 10BIT DUAL 125MSPS 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時(shí)間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
| AD9763ASTZKL1 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
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