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參數資料
| 型號： | AD9763 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 10-Bit, 125 MSPS Dual TxDAC+ D/A Converter |
| 中文描述： | 10位，125 MSPS的TxDAC系列雙D / A轉換 |
| 文件頁數： | 12/28頁 |
| 文件大?。?/td> | 460K |
| 代理商： | AD9763 |
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REV. B
AD9763
–
12
–
INTERLEAVED MODE TIMING
For the following section, refer to Figure 25.
When the MODE pin is at Logic 0, the AD9763 operates in
interleaved mode. WRT1 now functions as IQWRT and CLK1
functions as IQCLK. WRT2 functions as IQSEL and CLK2
functions as IQRESET.
Data enters the device on the rising edge of IQWRT. The logic
level of IQSEL will steer the data to either Channel Latch 1
(IQSEL = 1) or to Channel Latch 2 (IQSEL = 0).
When IQRESET is high, IQCLK is disabled. When IQRESET
goes low, the following rising edge on IQCLK will update both
DAC latches with the data present at their inputs. In the inter-
leaved mode, IQCLK is divided by 2 internally. Following this
first rising edge, the DAC latches will only be updated on every
other rising edge of IQCLK. In this way, IQRESET can be
used to synchronize the routing of the data to the DACs.
As with the dual port mode, IQCLK should occur before or
simultaneously with IQWRT.
IQSEL
IQWRT
DAC1
LATCH
DAC1
INTERLEAVED
DATA IN, PORT 1
DEINTERLEAVED
DATA OUT
IQCLK
IQRESET
DAC2
LATCH
DAC2
2
PORT 1
INPUT
LATCH
PORT 2
INPUT
LATCH
Figure 25. Latch Structure Interleaved Mode
Timing specifications for interleaved mode are given in Figures
26 and 27.
The digital inputs are CMOS-compatible with logic thresholds,
V
THRESHOLD
, set to approximately half the digital positive supply
(DVDD) or
V
THRESHOLD
= DVDD/2
(
±
20
%
)
DATA IN
IQWRT
IQCLK
IOUTA
OR
IOUTB
t
LPW
t
PD
t
S
t
H
t
CPW
Figure 26. Interleaved Mode Timing
D1
D2
D3
D4
D5
INTERLEAVED
DATA
xx
xx
D1
D2
D3
D4
xx
(WRT2) IQSEL
(WRT1) IQWRT
(CLK1) IQCLK
(EXTERNAL)
(CLK2)
IQRESET
DAC OUTPUT
PORT 1
DAC OUTPUT
PORT 2
IQCLK 2
(EXTERNAL)
Figure 27. Interleaved Mode Timing
The internal digital circuitry of the AD9763 is capable of oper-
ating over a digital supply range of 3 V to 5.5 V. As a result, the
digital inputs can also accommodate TTL levels when DVDD is
set to accommodate the maximum high level voltage of the TTL
drivers V
OH
(MAX). A DVDD of 3 V to 3.3 V will typically
ensure proper compatibility with most TTL logic families. Fig-
ure 28 shows the equivalent digital input circuit for the data and
clock inputs. The sleep mode input is similar with the excep-
tion that it contains an active pull-down circuit, thus ensuring
that the AD9763 remains enabled if this input is left discon-
nected.
Since the AD9763 is capable of being clocked up to 125 MSPS,
the quality of the clock and data input signals are important in
achieving the optimum performance. Operating the AD9763
with reduced logic swings and a corresponding digital supply
(DVDD) will result in the lowest data feedthrough and on-chip
digital noise. The drivers of the digital data interface circuitry
should be specified to meet the minimum setup and hold times
of the AD9763 as well as its required min/max input logic level
thresholds.
Digital signal paths should be kept short and run lengths matched
to avoid propagation delay mismatch. The insertion of a low
value resistor network (i.e., 20
to 100
) between the AD9763
digital inputs and driver outputs may be helpful in reducing any
overshooting and ringing at the digital inputs that contribute to
digital feedthrough. For longer board traces and high data up-
date rates, stripline techniques with proper impedance and
termination resistors should be considered to maintain “clean”
digital inputs.
The external clock driver circuitry should provide the AD9763
with a low jitter clock input meeting the min/max logic levels
while providing fast edges. Fast clock edges will help minimize
any jitter that will manifest itself as phase noise on a recon-
structed waveform. Thus, the clock input should be driven by
the fastest logic family suitable for the application.
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| AD9763-EB | 10-Bit, 125 MSPS Dual TxDAC+ D/A Converter |
| AD9763AST | 10-Bit, 125 MSPS Dual TxDAC+ D/A Converter |
| AD9764 | 14-Bit, 125 MSPS TxDAC D/A Converter |
| AD9764-EB | 14-Bit, 125 MSPS TxDAC D/A Converter |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9763_11 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-/12-/14-Bit, 125 MSPS Dual TxDAC Digital-to-Analog Converters |
| AD9763AST | 制造商:Analog Devices 功能描述:DAC 2-CH Segment 10-bit 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:10 BIT, 125 MSPS DUAL TXDAC+ - Tape and Reel 制造商:Analog Devices 功能描述:IC 10-BIT DAC |
| AD9763ASTRL | 制造商:Analog Devices 功能描述:DAC 2-CH Segment 10-bit 48-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:10 BIT, 125 MSPS DUAL TXDAC+ - Tape and Reel |
| AD9763ASTZ | 功能描述:IC DAC 10BIT DUAL 125MSPS 48LQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 數模轉換器 系列:TxDAC+® 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 設置時間:4µs 位數:12 數據接口:串行 轉換器數目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應商設備封裝:8-uMAX 包裝:管件 輸出數目和類型:2 電壓，單極 采樣率（每秒）:* 產品目錄頁面:1398 (CN2011-ZH PDF) |
| AD9763ASTZKL1 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
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