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參數(shù)資料
| 型號： | AD9761ARS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Dual 10-Bit TxDAC+⑩ with 2x Interpolation Filters |
| 中文描述： | DUAL, PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 10-BIT DAC, PDSO28 |
| 封裝： | SSOP-28 |
| 文件頁數(shù)： | 12/23頁 |
| 文件大?。?/td> | 246K |
| 代理商： | AD9761ARS |
AD9761
–12–
REV. A
50pF
CURRENT
SOURCE
ARRAY
+1.2V REF
REFIO
FSADJ
REFLO
COMP2
AVDD
I
REF
=
V
REF
/R
SET
AVDD
R
SET
EXT.
V
REF
AVDD
0.1
m
F
AD9761
+
–
Figure 25. External Reference Configuration
REFERENCE CONTROL AMPLIFIER
The AD9761 also contains an internal control amplifier which is
used to simultaneously regulate both DAC’s full-scale output
current, I
OUTFS
. Since the I and Q I
OUTFS
are derived from the
same voltage reference and control circuitry, excellent gain
matching is ensured. The control amplifier is configured as a
V-I converter as shown in Figure 25 such that its current out-
put, I
REF
, is determined by the ratio of the V
REFIO
and an exter-
nal resistor, R
SET
, as stated in Equation (4). I
REF
is copied over
to the segmented current sources with the proper scaling factor
to set I
OUTFS
as stated in Equation (3).
The control amplifier allows a wide (10:1) adjustment span of
I
OUTFS
over a 1mA to 10 mA range by setting I
REF
between
62.5
A and 625
μ
A. The wide adjustment span of I
OUTFS
pro-
vides several application benefits. The first benefit relates di-
rectly to the power dissipation of the AD9761’s analog supply,
AVDD, which is proportional to I
OUTFS
(refer to the POWER
DISSIPATION section). The second benefit relates to the
20 dB adjustment span which may be useful for system gain
control purposes.
Optimum noise and dynamic performance for the AD9761 is
obtained with a 0.1
μ
F external capacitor installed between
COMP2 and AVDD. The bandwidth of the reference control
amplifier is limited to approximately 5 kHz with a 0.1
μ
F ca-
pacitor installed. Since the –3 dB bandwidth corresponds to the
dominant pole and hence its dominant time constant, the set-
tling time of the control amplifier to a stepped reference input
response can be easily determined. Note, the output of the
control amplifier, COMP2, is internally compensated via a
50 pF capacitor thus ensuring its stability if no external capaci-
tor is added.
Depending on the requirements of the application, I
REF
can be
adjusted by varying either R
SET
, or in the external reference
mode, by varying the REFIO voltage. I
REF
can be varied for a
fixed R
SET
by disabling the internal reference and varying the
voltage of REFIO over its compliance range of 1.25 V to 0.10 V.
REFIO can be driven by a single-supply amplifier or DAC thus
allowing I
REF
to be varied for a fixed R
SET
. Since the input im-
pedance of REFIO is approximately 1 M
, a simple, low cost
R-2R ladder DAC configured in the voltage mode topology may
be used to control the gain. This circuit is shown in Figure 26
using the AD7524 and an external 1.2 V reference, the AD1580.
ANALOG OUTPUTS
As previously stated, both the I and Q DACs produce two
complementary current outputs which may be configured for
single-end or differential operation. I
IOUTA
and I
IOUTB
can be
converted into complementary single-ended voltage outputs,
V
IOUTA
and V
IOUTB
, via a load resistor, R
LOAD
, as described in
the DAC TRANSFER SECTION by Equations 5 through 8.
The differential voltage, V
IDIFF
, existing between V
IOUTA
and
V
IOUTB
can also be converted to a single-ended voltage via a
transformer or differential amplifier configuration.
Figure 27 shows an equivalent circuit of the AD9761’s I (or Q)
DAC output. It consists of a parallel array of PMOS current
sources in which each current source is switched to either
IOUTA or IOUTB via a differential PMOS switch. As a result,
the equivalent output impedance of IOUTA and IOUTB re-
mains quite high (i.e., >100 k
and 5 pF).
AD9761
AVDD
R
LOAD
R
LOAD
IOUTA
IOUTB
Figure 27. Equivalent Circuit of the AD9761 DAC Output
IOUTA and IOUTB have a negative and positive voltage com-
pliance range which must be adhered to achieve optimum per-
formance. The negative output compliance range of –1 V is set
by the breakdown limits of the CMOS process. Operation be-
yond this maximum limit may result in a breakdown of the
output stage.
50pF
CURRENT
SOURCE
ARRAY
+1.2V REF
REFIO
FSADJ
REFLO
COMP2
AVDD
AVDD
AD1580
1.2V
OPTIONAL
BANDLIMITING
CAPACITOR
I
REF
=
V
REF
/R
SET
AVDD
R
SET
0.1V TO 1.2V
R
FB
V
DD
OUT1
OUT2
AGND
V
REF
AD7524
DB7–DB0
+
–
AD9761
Figure 26. Single-Supply Gain Control Circuit
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9761-ARS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10-Bit Digital-to-Analog Converter |
| AD9761ARSRL | 功能描述:IC DAC 10BIT DUAL 40MSPS 28-SSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD9761ARSZ | 功能描述:IC DAC 10BIT DUAL 40MSPS 28-SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時(shí)間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
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| AD9761-EB | 制造商:Analog Devices 功能描述:Evaluation Board For AD9761 制造商:Analog Devices 功能描述:DEV TOOLS, EVAL BD FOR AD9761 - Bulk 制造商:Analog Devices 功能描述:SEMICONDUCTOR ((NS)) |
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