參數(shù)資料
型號(hào)： AD9761
廠商： Analog Devices, Inc.
英文描述： Dual 10-Bit TxDAC with 23 Interpolation Filters(內(nèi)插濾波器的雙10位D/A轉(zhuǎn)換器)
中文描述： 雙10與23位插值濾波器TxDAC系列（內(nèi)插濾波器的雙10位的D / A轉(zhuǎn)換器）
文件頁(yè)數(shù)： 13/24頁(yè)
文件大?。?/td> 294K
代理商： AD9761
AD9761
–13–
REV. 0
T he positive output compliance range is slightly dependent on
the full-scale output current, I
OUT FS
. It degrades slightly from
its nominal 1.25 V for an IOUT FS = 10 mA to 1.00 V for an
IOUT FS = 2 mA. Applications requiring the AD9761’s output
(i.e., V
OUT A
and/or V
OUT B
) to extend to its output compliance
range should size R
LOAD
accordingly. Operation beyond this
compliance range will adversely affect the AD9761’s linearity
performance and subsequently degrade its distortion perfor-
mance. Note, the optimum distortion performance of the
AD9761 is obtained by restricting its output(s) as seen at
IOUT (A/B) and QOUT (A/B) to within
±
0.5 V.
DIGIT AL INPUT S AND INT E RLE AVE D INT E RFACE
CONSIDE RAT IONS
T he AD9761 digital interface consists of 10 data input pins, a
clock input pin, and three control pins. It is designed to support
a clock rate up to 40 MSPS. T he 10-bit parallel data inputs
follow standard positive binary coding, where DB9 is the most
significant bit (MSB) and DB0 is the least significant bit (LSB).
IOUT A (or QOUT A) produces a full-scale output current when
all data bits are at logic 1. IOUT B (or QOUT B) produces a
complementary output, with the full-scale current split between
the two outputs as a function of the input code.
STATE
MACHINE
"I" AND "Q" DATA
CLOCK
SELECT
RESET/SLEEP
WRITE
"Q" DATA
CLOCK
2
"I" DATA
"I"
INPUT
REGISTER
"I"
FILTER
REGISTER
"Q"
INPUT
REGISTER
"Q"
FILTER
REGISTER
Figure 28. Block Diagram of Digital Interface
T he AD9761 interfaces with a single 10-bit digital input bus
that supports interleaved I and Q input data. Figure 28 shows a
simplified block diagram of the digital interface circuitry consist-
ing of two banks of edge triggered registers, two multiplexers,
and a state machine. Interleaved I and Q input data is presented
at the DAT A input bus, where it is then latched into the se-
lected I or Q input register on the rising edge of the WRIT E
input. T he output of these input registers is transferred in pairs
to their respective interpolator filters’ register after each Q write
on the rising edge of the CLOCK input (refer to T iming Dia-
gram in Figure 2). A state machine ensures the proper pairing of
I and Q input data to the interpolation filter’s inputs.
T he SELECT signal at the time of the rising edge of the WRIT E
signal determines which input register latches the input data. If
SELECT is high around the rising edge of WRIT E the data is
latched into the I register of the AD9761. If SELECT is low
around the rising edge of the WRIT E, the data is latched into
the Q register of the AD9761. If SELECT is kept in one state
while data is repeatedly writing to the AD9761, the data will be
written into the selected filter register at half the input data rate
since the data is always assumed to be interleaved.
T he state machine controls the generation of the divided clock
and hence pairing of I and Q data inputs. After the AD9761 is
reset, the state machine keeps track of the paired I and Q data.
T he state transition diagram is shown in Figure 29 in which all
the states are defined. A transition in state occurs upon the
rising edge of CLOCK and is function of the current state as
well as status of SELECT , WRIT E and SLEEP. T he state ma-
chine is reset on the first rising CLOCK edge while RESET
remains high. Upon RESET returning low, a state transition will
occur on the first rising edge of CLOCK . T he most recent I and Q
data samples are transferred to the correct interpolation filter
only upon entering state FILT ER DAT A.
ONE, I
RESET
FILTER
DATA
I.Q or I.Q or N
I.Q
I.Q
N
I.Q
I = WRITE & SELECT FOLLOWED BY A CLOCK
Q = WRITE & SELECT FOLLOWED BY A CLOCK
N = CLOCK ONLY, NO WRITE
I.Q
I.Q
I.Q
I.Q
Figure 29. State Transition Diagram of AD9761 Digital
Interface
T wo examples help illustrate the digital timing and control
requirements to ensure proper pairing of I and Q data. In the
first example, the AD9761 is assumed to interface with a host
processor on a dedicated data bus. In the second example, two
AD9761 devices sharing the same data bus are required to be
simultaneously updated. In both examples, the state machine is
reset by asserting a Logic Level “1” to the RESET /SLEEP input
for a duration of one clock cycle.
In the first example, shown in Figure 30a, WRIT E and CLOCK
are tied together while SELECT is updated at the same instance
as DAT A. Since SELECT is high upon RESET returning low,
I data is latched into the I input register on the first rising
WRIT E. On the next rising WRIT E edge, the Q data is latched
into its input register and the outputs of both input registers are
latched into their respective I and Q filter registers. T he se-
quence of events is repeated on the next rising WRIT E edge
with the new I data being latched into the I input register.
In the second example, shown in Figure 30b, two AD9761
devices (i.e., A and B) share the same data bus as well as RE-
SET , SELECT and CLOCK inputs. Both devices are simulta-
neously reset on the first rising edge of CLOCK while RESET is
high. T he I and Q digital data is organized in pairs, forming
groups of four data samples. T hese pairs of I and Q samples are
simultaneously loaded into their respective devices’ I and Q
filter registers.
SEL ECT determines whether a pair of I or Q data is present
on the data bus. WRIT E A latches in I or Q samples pertaining
to device A, while WRIT E B latches in I or Q samples pertain-
ing to device B. WRIT E A and B, for instance, could be gener-
ated by gating the host processors available data clock with
相關(guān)PDF資料
PDF描述
AD9762 Analog Devices: Data Converters: DAC 12-Bit, 10 ns to 100 ns Converters Selection Table
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AD9765 Analog Devices: Data Converters: DAC 12-Bit, 10 ns to 100 ns Converters Selection Table
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