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| 型號： | AD9761 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual 10-Bit TxDAC with 23 Interpolation Filters(內(nèi)插濾波器的雙10位D/A轉(zhuǎn)換器) |
| 中文描述： | 雙10與23位插值濾波器TxDAC系列（內(nèi)插濾波器的雙10位的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 12/24頁 |
| 文件大?。?/td> | 294K |
| 代理商： | AD9761 |
AD9761
–12–
REV. 0
50pF
CURRENT
SOURCE
ARRAY
+1.2V REF
REFIO
FSADJ
REFLO
COMP2
AVDD
I
REF
=
V
REF
/R
SET
AVDD
R
SET
EXT.
V
REF
AVDD
0.1 F
AD9761
+
–
Figure 25. External Reference Configuration
RE FE RE NCE CONT ROL AMPLIFIE R
T he AD9761 also contains an internal control amplifier which is
used to simultaneously regulate both DAC’s full-scale output
current, I
OUT FS
. Since the I and Q I
OUT FS
are derived from the
same voltage reference and control circuitry, excellent gain
matching is ensured. T he control amplifier is configured as a
V-I converter as shown in Figure 25 such that its current out-
put, I
REF
, is determined by the ratio of the V
REFIO
and an exter-
nal resistor, R
SET
, as stated in Equation (4). I
REF
is copied over
to the segmented current sources with the proper scaling factor
to set I
OUT FS
as stated in Equation (3).
T he control amplifier allows a wide (10:1) adjustment span of
I
OUT FS
over a 1 mA to 10 mA range by setting I
REF
between
62.5
μ
A and 625
μ
A. T he wide adjustment span of I
OUT FS
pro-
vides several application benefits. T he first benefit relates di-
rectly to the power dissipation of the AD9761’s analog supply,
AVDD, which is proportional to I
OUT FS
(refer to the POWER
DISSIPAT ION section). T he second benefit relates to the
20 dB adjustment span which may be useful for system gain
control purposes.
Optimum noise and dynamic performance for the AD9761 is
obtained with a 0.1
μ
F external capacitor installed between
COMP2 and AVDD. T he bandwidth of the reference control
amplifier is limited to approximately 5 kHz with a 0.1
μ
F ca-
pacitor installed. Since the –3 dB bandwidth corresponds to the
dominant pole and hence its dominant time constant, the set-
tling time of the control amplifier to a stepped reference input
response can be easily determined. Note, the output of the
control amplifier, COMP2, is internally compensated via a
50 pF capacitor thus ensuring its stability if no external capaci-
tor is added.
Depending on the requirements of the application, I
REF
can be
adjusted by varying either R
SET
, or in the external reference
mode, by varying the REFIO voltage. I
REF
can be varied for a
fixed R
SET
by disabling the internal reference and varying the
voltage of REFIO over its compliance range of 1.25 V to 0.10 V.
REFIO can be driven by a single-supply amplifier or DAC thus
allowing I
REF
to be varied for a fixed R
SET
. Since the input im-
pedance of REFIO is approximately 1 M
, a simple, low cost
R-2R ladder DAC configured in the voltage mode topology may
be used to control the gain. T his circuit is shown in Figure 26
using the AD7524 and an external 1.2 V reference, the AD1580.
ANALOG OUT PUT S
As previously stated, both the I and Q DACs produce two
complementary current outputs which may be configured for
single-end or differential operation. I
IOUT A
and I
IOUT B
can be
converted into complementary single-ended voltage outputs,
V
IOUT A
and V
IOUT B
, via a load resistor, R
LOAD
, as described in
the DAC T RANSFER SECT ION by Equations 5 through 8.
T he differential voltage, V
IDIFF
, existing between V
IOUT A
and
V
IOUT B
can also be converted to a single-ended voltage via a
transformer or differential amplifier configuration.
Figure 27 shows an equivalent circuit of the AD9761’s I (or Q)
DAC output. It consists of a parallel array of PMOS current
sources in which each current source is switched to either
IOUT A or IOUT B via a differential PMOS switch. As a result,
the equivalent output impedance of IOUT A and IOUT B re-
mains quite high (i.e., >100 k
and 5 pF).
AD9761
AVDD
R
LOAD
R
LOAD
IOUTA
IOUTB
Figure 27. Equivalent Circuit of the AD9761 DAC Output
IOUT A and IOUT B have a negative and positive voltage com-
pliance range which must be adhered to achieve optimum per-
formance. T he negative output compliance range of –1 V is set
by the breakdown limits of the CMOS process. Operation be-
yond this maximum limit may result in a breakdown of the
output stage.
50pF
CURRENT
SOURCE
ARRAY
+1.2V REF
REFIO
FS ADJ
REFLO
COMP2
AVDD
AVDD
AD1580
1.2V
OPTIONAL
BANDLIMITING
CAPACITOR
I
REF
=
V
REF
/R
SET
AVDD
R
SET
0.1V TO 1.2V
R
FB
V
DD
OUT1
OUT2
AGND
V
REF
AD7524
DB7–DB0
+
–
AD9761
Figure 26. Single-Supply Gain Control Circuit
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