參數資料
型號: AD9754ARUZ
廠商: Analog Devices Inc
文件頁數: 3/24頁
文件大小: 0K
描述: IC DAC 14BIT 125MSPS 28-TSSOP
產品培訓模塊: Data Converter Fundamentals
DAC Architectures
標準包裝: 50
系列: TxDAC®
設置時間: 35ns
位數: 14
數據接口: 并聯
轉換器數目: 1
電壓電源: 模擬和數字
功率耗散(最大): 220mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 28-TSSOP
包裝: 管件
輸出數目和類型: 1 電流,單極;1 電流,雙極
采樣率(每秒): 125M
產品目錄頁面: 785 (CN2011-ZH PDF)
AD9754
–11–
REV. A
input impedance of REFIO is approximately 1 M
, a simple,
low cost R-2R ladder DAC configured in the voltage mode
topology may be used to control the gain. This circuit is shown
in Figure 19 using the AD7524 and an external 1.2 V reference,
the AD1580.
The second method may be used in a dual-supply system in
which the common-mode voltage of REFIO is fixed, and IREF is
varied by an external voltage, VGC, applied to RSET via an ampli-
fier. An example of this method is shown in Figure 25 in which
the internal reference is used to set the common-mode voltage
of the control amplifier to 1.20 V. The external voltage, VGC, is
referenced to ACOM and should not exceed 1.2 V. The value of
RSET is such that IREFMAX and IREFMIN do not exceed 62.5
A
and 625
A, respectively. The associated equations in Figure 20
can be used to determine the value of RSET.
150pF
+1.2V REF
AVDD
REFLO
CURRENT
SOURCE
ARRAY
AVDD
REFIO
FS ADJ
RSET
AD9754
IREF
VGC
1 F
IREF = (1.2 – VGC)/RSET
WITH VGC
VREFIO AND 62.5 A
IREF
625A
Figure 20. Dual-Supply Gain Control Circuit
ANALOG OUTPUTS
The AD9754 produces two complementary current outputs,
IOUTA and IOUTB, which may be configured for single-end
or differential operation. IOUTA and IOUTB can be converted
into complementary single-ended voltage outputs, VOUTA and
VOUTB, via a load resistor, RLOAD, as described in the DAC
Transfer Function section by Equations 5 through 8. The
differential voltage, VDIFF, existing between VOUTA and VOUTB
can also be converted to a single-ended voltage via a transformer
or differential amplifier configuration.
Figure 21 shows the equivalent analog output circuit of the
AD9754 consisting of a parallel combination of PMOS differen-
tial current switches associated with each segmented current
source. The output impedance of IOUTA and IOUTB is deter-
mined by the equivalent parallel combination of the PMOS
switches and is typically 100 k
in parallel with 5 pF. Due to
the nature of a PMOS device, the output impedance is also
slightly dependent on the output voltage (i.e., VOUTA and VOUTB)
and, to a lesser extent, the analog supply voltage, AVDD, and
full-scale current, IOUTFS. Although the output impedance’s signal
dependency can be a source of dc nonlinearity and ac linearity
(i.e., distortion), its effects can be limited if certain precautions
are noted.
AD9754
AVDD
IOUTA
IOUTB
RLOAD
Figure 21. Equivalent Analog Output Circuit
IOUTA and IOUTB also have a negative and positive voltage
compliance range. The negative output compliance range of
–1.0 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a break-
down of the output stage and affect the reliability of the AD9754.
The positive output compliance range is slightly dependent on
the full-scale output current, IOUTFS. It degrades slightly from its
nominal 1.25 V for an IOUTFS = 20 mA to 1.00 V for an IOUTFS =
2 mA. Operation beyond the positive compliance range will
induce clipping of the output signal which severely degrades
the AD9754’s linearity and distortion performance.
For applications requiring the optimum dc linearity, IOUTA
and/or IOUTB should be maintained at a virtual ground via an
I-V op amp configuration. Maintaining IOUTA and/or IOUTB
at a virtual ground keeps the output impedance of the AD9754
fixed, significantly reducing its effect on linearity. However,
it does not necessarily lead to the optimum distortion perfor-
mance due to limitations of the I-V op amp. Note that the
INL/DNL specifications for the AD9754 are measured in
this manner using IOUTA. In addition, these dc linearity
specifications remain virtually unaffected over the specified
power supply range of +4.5 V to +5.5 V.
Operating the AD9754 with reduced voltage output swings at
IOUTA and IOUTB in a differential or single-ended output
configuration reduces the signal dependency of its output
impedance thus enhancing distortion performance. Although
the voltage compliance range of IOUTA and IOUTB extends
from –1.0 V to +1.25 V, optimum distortion performance is
achieved when the maximum full-scale signal at IOUTA and
IOUTB does not exceed approximately 0.5 V. A properly se-
lected transformer with a grounded center-tap will allow the
AD9754 to provide the required power and voltage levels to
different loads while maintaining reduced voltage swings at
IOUTA and IOUTB. DC-coupled applications requiring a
differential or single-ended output configuration should size
RLOAD accordingly. Refer to Applying the AD9754 section for
examples of various output configurations.
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