參數(shù)資料
型號: AD9754ARUZ
廠商: Analog Devices Inc
文件頁數(shù): 11/24頁
文件大?。?/td> 0K
描述: IC DAC 14BIT 125MSPS 28-TSSOP
產(chǎn)品培訓模塊: Data Converter Fundamentals
DAC Architectures
標準包裝: 50
系列: TxDAC®
設(shè)置時間: 35ns
位數(shù): 14
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
功率耗散(最大): 220mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應商設(shè)備封裝: 28-TSSOP
包裝: 管件
輸出數(shù)目和類型: 1 電流,單極;1 電流,雙極
采樣率(每秒): 125M
產(chǎn)品目錄頁面: 785 (CN2011-ZH PDF)
AD9754
–19–
REV. A
Figure 37 shows the AD9754 reconstructing a wideband, or
W-CDMA test vector with a bandwidth of 5 MHz, centered at
15.625 MHz and being sampled at 62.5 MSPS. ACP for the
given test vector is measured at 70 dB.
FREQUENCY – MHz
REFERENCE
LEVEL
dBm
–30
–50
–110
–70
–90
13.125
15.625
18.125
–40
–60
–80
–100
–20
–120
Figure 37. CDMA Signal, Sampled at 65 MSPS, Adjacent
Channel Power >70 dB
AD9754 EVALUATION BOARD
General Description
The AD9754-EB is an evaluation board for the AD9754 14-bit
DAC converter. Careful attention to layout and circuit design,
combined with a prototyping area, allows the user to easily and
effectively evaluate the AD9754 in any application where high
resolution, high speed conversion is required.
This board allows the user the flexibility to operate the AD9754
in various configurations. Possible output configurations in-
clude transformer coupled, resistor terminated, inverting/
noninverting and differential amplifier outputs. The digital inputs
are designed to be driven directly from various word generators
with the onboard option to add a resistor network for proper
load termination. Provisions are also made to operate the
AD9754 with either the internal or external reference or to
exercise the power-down feature.
Refer to the application note AN-420 for a thorough description
and operating instructions for the AD9754 evaluation board.
AD9754
(“I DAC”)
AD9754
(“Q DAC”)
IOUTA
IOUTB
QOUTA
QOUTB
DCOM
FSADJ
REFIO
SLEEP
RSET2
1.9k
0.1 F
CLK
Q DATA
INPUT
I DATA
INPUT
DVDD
AVDD
100W
500
100
CFILTER
100
500
634
+3V
IIPP
IIPN
IIQP
IIQN
AD6122
REFLO
ACOM
REFLO
AVDD
REFIO
FSADJ
RSET1
2k
RCAL
220
U1
U2
AVDD
LATCHES
500
DAC
LATCHES
100
2
TEMPERATURE
COMPENSATION
GAIN
CONTROL
SCALE
FACTOR
REFIN
VGAIN
GAIN
CONTROL
LOIPP
LOIPN
TXOPP
TXOPN
VCC
PHASE
SPLITTER
MODOPP
MODOPN
Figure 36. CDMA Transmit Application Using AD9754
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