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參數(shù)資料
| 型號(hào)： | AD9753-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit, 300 MSPS High-Speed TxDAC+?? D/A Converter |
| 中文描述： | 12位，300 MSPS的高速TxDAC系列？？ D / A轉(zhuǎn)換 |
| 文件頁(yè)數(shù)： | 3/26頁(yè) |
| 文件大小： | 904K |
| 代理商： | AD9753-EB |
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REV. 0
–3–
AD9753
(T
MIN
to T
MAX
, AVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 0 V, CLKVDD = 3.3 V, I
OUTFS
= 20 mA,
Differential Transformer Coupled Output, 50 Doubly Terminated, unless otherwise noted.)
Min
DYNAMIC SPECIFICATIONS
Parameter
Typ
Max
Unit
DYNAMIC PERFORMANCE
Maximum Output Update Rate (f
DAC
)
Output Settling Time (t
ST
) (to 0.1%)
1
Output Propagation Delay (t
PD
)
1
Glitch Impulse
1
Output Rise Time (10% to 90%)
1
Output Fall Time (10% to 90%)
1
Output Noise (I
OUTFS
= 20 mA)
Output Noise (I
OUTFS
= 2 mA)
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
f
DAC
= 100 MSPS; f
OUT
= 1.00 MHz
0 dBFS Output
–6 dBFS Output
–12 dBFS Output
f
DATA
= 65 MSPS; f
OUT
= 1.1 MHz
2
f
DATA
= 65 MSPS; f
OUT
= 5.1 MHz
2
f
DATA
= 65 MSPS; f
OUT
= 10.1 MHz
2
f
DATA
= 65 MSPS; f
OUT
= 20.1 MHz
2
f
DATA
= 65 MSPS; f
OUT
= 30.1 MHz
2
f
DAC
= 200 MSPS; f
OUT
= 1.1 MHz
f
DAC
= 200 MSPS; f
OUT
= 11.1 MHz
f
DAC
= 200 MSPS; f
OUT
= 31.1 MHz
f
DAC
= 200 MSPS; f
OUT
= 51.1 MHz
f
DAC
= 200 MSPS; f
OUT
= 71.1 MHz
f
DAC
= 300 MSPS; f
OUT
= 1.1 MHz
f
DAC
= 300 MSPS; f
OUT
= 26.1 MHz
f
DAC
= 300 MSPS; f
OUT
= 51.1 MHz
f
DAC
= 300 MSPS; f
OUT
= 101.1 MHz
f
DAC
= 300 MSPS; f
OUT
= 141.1 MHz
Spurious-Free Dynamic Range within a Window
f
DAC
= 100 MSPS; f
OUT
= 1 MHz; 2 MHz Span
0 dBFS Output
f
DAC
= 65 MSPS; f
OUT
= 5.02 MHz; 2 MHz Span
f
DAC
= 150 MSPS; f
OUT
= 5.04 MHz; 4 MHz Span
Total Harmonic Distortion
f
DAC
= 100 MSPS; f
OUT
= 1.00 MHz
0 dBFS
f
DAC
= 65 MHz; f
OUT
= 2.00 MHz
f
DAC
= 160 MHz; f
OUT
= 2.00 MHz
Multitone Power Ratio (Eight Tones at 110 kHz Spacing)
f
DAC
= 65 MSPS; f
OUT
= 2.00 MHz to 2.77 MHz
0 dBFS Output
–6 dBFS Output
–12 dBFS Output
300
MSPS
ns
ns
pV-s
ns
ns
pA/
√
Hz
pA/
√
Hz
11
1
5
2.5
2.5
50
30
72
82
76
76
77
77
76
72
68
78
75
70
70
67
78
69
65
59
58
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
82.5
92
85
85
dBc
dBc
dBc
–82
–76
–76
–71
dBc
dBc
dBc
73
71
69
dBc
dBc
dBc
NOTES
1
Measured single-ended into 50
load.
2
Single-Port Mode (PLL disabled, DIV0 = 1, DIV1 = 0, data on Port 1).
Specifications subject to change without notice.
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