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參數(shù)資料
| 型號(hào)： | AD9748ACPZRL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT 210MSPS 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 系列： | TxDAC® |
| 設(shè)置時(shí)間： | 11ns |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 145mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 210M |
Data Sheet
AD9748
Rev. B | Page 13 of 24
The output impedance of IOUTA and IOUTB is determined
by the equivalent parallel combination of the PMOS switches
associated with the current sources and is typically 100 k in
parallel with 5 pF. It is also slightly dependent on the output
voltage (that is, VOUTA and VOUTB) due to the nature of a PMOS
device. As a result, maintaining IOUTA and/or IOUTB at a
virtual ground via an I-V op amp configuration results in the
optimum dc linearity. Note that the INL/DNL specifications for
the AD9748 are measured with IOUTA maintained at a virtual
ground via an op amp.
IOUTA and IOUTB also have a negative and positive voltage
compliance range that must be adhered to in order to achieve
optimum performance. The negative output compliance range
of 1 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit can result in a breakdown
of the output stage and affect the reliability of the AD9748.
The positive output compliance range is slightly dependent on
the full-scale output current, IOUTFS. It degrades slightly from its
nominal 1.2 V for an IOUTFS = 20 mA to 1 V for an IOUTFS = 2 mA.
The optimum distortion performance for a single-ended or
differential output is achieved when the maximum full-scale
signal at IOUTA and IOUTB does not exceed 0.5 V.
DIGITAL INPUTS
The AD9748 digital section consists of eight input bit channels
and a clock input. The 8-bit parallel data inputs follow standard
positive binary coding, where DB7 is the most significant bit
(MSB) and DB0 is the least significant bit (LSB). IOUTA
produces a full-scale output current when all data bits are at
Logic 1. IOUTB produces a complementary output with the
full-scale current split between the two outputs as a function of
the input code.
DVDD
DIGITAL
INPUT
03211-016
Figure 19. Equivalent Digital Input
The digital interface is implemented using an edge-triggered
master/slave latch. The DAC output updates on the rising edge
of the clock and is designed to support a clock rate as high as
210 MSPS. The clock can be operated at any duty cycle that
meets the specified latch pulse width. The setup and hold times
can also be varied within the clock cycle as long as the specified
minimum times are met, although the location of these
transition edges can affect digital feedthrough and distortion
performance. Best performance is typically achieved when the
input data transitions on the falling edge of a 50% duty cycle clock.
CLOCK INPUT
A configurable clock input allows for one single-ended and two
differential modes. The mode selection is controlled by the
CMODE input, as summarized in Table 6. Connecting CMODE
to CLKCOM selects the single-ended clock input. In this mode,
the CLK+ input is driven with rail-to-rail swings and the CLK
input is left floating. If CMODE is connected to CLKVDD, then
the differential receiver mode is selected. In this mode, both
inputs are high impedance. The final mode is selected by
floating CMODE. This mode is also differential, but internal
terminations for positive emitter-coupled logic (PECL) are
activated. There is no significant performance difference
between any of the three clock input modes.
Table 6. Clock Mode Selection
CMODE Pin
Clock Input Mode
CLKCOM
Single-ended
CLKVDD
Differential
Float
PECL
In the single-ended input mode, the CLK+ pin must be driven
with rail-to-rail CMOS levels. The quality of the DAC output is
directly related to the clock quality, and jitter is a key concern.
Any noise or jitter in the clock translates directly into the DAC
output. Optimal performance is achieved if the clock input has
a sharp rising edge, because the DAC latches are positive edge
triggered.
In the differential input mode, the clock input functions as a
high impedance differential pair. The common-mode level of
the CLK+ and CLK inputs can vary from 0.75 V to 2.25 V, and
the differential voltage can be as low as 0.5 V p-p. This mode
can be used to drive the clock with a differential sine wave,
because the high gain bandwidth of the differential inputs
convert the sine wave into a single-ended square wave
internally.
The final clock mode allows for a reduced external component
count when the DAC clock is distributed on the board using
PECL logic. The internal termination configuration is shown in
Figure 20. These termination resistors are untrimmed and can
vary up to ±20%. However, matching between the resistors
should generally be better than ±1%.
CLK+
TO DAC CORE
CLK–
VTT = 1.3V NOM
50
50
AD9748
CLOCK
RECEIVER
03211-017
Figure 20. Clock Termination in PECL Mode
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