- 您現在的位置：買賣IC網 > PDF目錄1988 > AD9653BCPZRL7-125 (Analog Devices Inc)IC ADC 16BIT 125MSPS SRL 48LFCSP PDF資料下載
參數資料
| 型號： | AD9653BCPZRL7-125 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 29/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 125MSPS SRL 48LFCSP |
| 標準包裝： | 750 |
| 位數： | 16 |
| 采樣率（每秒）： | 125M |
| 數據接口： | LVDS，串行，SPI? |
| 轉換器數目： | 4 |
| 功率耗散（最大）： | 708mW |
| 電壓電源： | 模擬和數字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-WFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 48-LFCSP-WQ（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數目和類型： | 4 個差分，單極 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁當前第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁
Data Sheet
AD9653
Rev. 0 | Page 35 of 40
ADDR
(Hex)
Parameter Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Comments
0x0B
Clock divide
(global)
Open
Clock divide ratio[2:0]
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
0x00
0x0C
Enhancement
control
Open
Chop
mode
0 = off
1 = on
Open
0x00
Enables/
disables chop
mode.
0x0D
Test mode (local
except for PN
sequence resets)
User input test mode
00 = single
01 = alternate
10 = single once
11 = alternate once
(affects user input test
mode only,
Bits[3:0] = 1000)
Reset
PN long
gen
Reset PN
short
gen
Output test mode[3:0] (local)
0000 = off (default)
0001 = midscale short
0010 = positive FS
0011 = negative FS
0100 = alternating checkerboard
0101 = PN 23 sequence
0110 = PN 9 sequence
0111 = one/zero word toggle
1000 = user input
1001 = 1-/0-bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency
0x00
When set, the
test data is
placed on the
output pins in
place of
normal data.
0x10
Offset adjust
(local)
8-bit device offset adjustment [7:0] (local)
Offset adjust in LSBs from +127 to 128 (twos complement format)
0x00
Device offset
trim.
0x14
Output mode
Open
LVDS-ANSI/
LVDS-IEEE
option
0 = LVDS-
ANSI
1 = LVDS-
IEEE
reduced
range link
(global)
see
Open
Output
invert
(local)
Open
Output
format
0 =
offset
binary
1 =
twos
comple-
ment
(global)
0x01
Configures
the outputs
and the
format of the
data.
0x15
Output adjust
Open
Output driver
termination[1:0]
00 = none
01 = 200 Ω
10 = 100 Ω
11 = 100 Ω
Open
Output
drive
0 = 1×
drive
1 = 2×
drive
0x00
Determines
LVDS or other
output
properties.
0x16
Output phase
Open
Input clock phase adjust[6:4]
(value is number of input clock
cycles of phase delay)
Output clock phase adjust[3:0]
(0000 through 1011)
0x03
On devices
that use
global clock
divide,
determines
which phase
of the divider
output is used
to supply the
output clock.
Internal
latching is
unaffected.
相關PDF資料 |
PDF描述 |
|---|---|
| AD9707BCPZRL7 | IC DAC TX 14BIT 175MSPS 32-LFCSP |
| AD9709ASTZRL | IC DAC 8BIT DUAL 125MSPS 48LQFP |
| AD9715BCPZ | IC DAC DUAL 10BIT LO PWR 40LFCSP |
| AD9726BSVZRL | IC DAC 16IT LVDS 400MSPS 80-TQFP |
| AD9736BBC | IC DAC 14BIT 1.2GSPS 160CSPBGA |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9655-125EBZ | 功能描述:AD9655 - 16 Bit 125M Samples per Second Analog to Digital Converter (ADC) Evaluation Board 制造商:analog devices inc. 系列:- 零件狀態(tài):有效 A/D 轉換器數:2 位數:16 采樣率（每秒）:125M 數據接口:LVDS - 串行，SPI 輸入范圍:2.8 Vpp 不同條件下的功率（典型值）:313mW @ 125MSPS 使用的 IC/零件:AD9655 所含物品:板 標準包裝:1 |
| AD9656BCPZ-125 | 制造商:Analog Devices 功能描述:16BIT 125MSPS 1.8V QUAD ADC W/SERIAL OUT - Trays 制造商:Analog Devices 功能描述:IC ADC 16BIT 125MSPS 56LFCSP |
| AD9656EBZ | 制造商:Analog Devices 功能描述:16BIT 125MSPS 1.8V QUAD ADC W/SERIAL OUT - Boxed Product (Development Kits) |
| AD9660 | 制造商:AD 制造商全稱:Analog Devices 功能描述:200 MHz Laser Diode Driver with Light Power Control |
| AD96606 | 制造商:AD 制造商全稱:Analog Devices 功能描述:200 MHz Laser Diode Driver with Light Power Control |
發(fā)布緊急采購，3分鐘左右您將得到回復。