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參數(shù)資料
型號： AD9653BCPZRL7-125
廠商： Analog Devices Inc
文件頁數(shù)： 24/40頁
文件大?。?/td> 0K
描述： IC ADC 16BIT 125MSPS SRL 48LFCSP
標(biāo)準(zhǔn)包裝： 750
位數(shù)： 16
采樣率（每秒）： 125M
數(shù)據(jù)接口： LVDS，串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 708mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-WFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-WQ（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個差分，單極
AD9653
Data Sheet
Rev. 0 | Page 30 of 40
The PN sequence short pattern produces a pseudorandom bit
sequence that repeats itself every 29 1 or 511 bits. A descrip-
tion of the PN sequence and how it is generated can be found in
Section 5.1 of the ITU-T 0.150 (05/96) standard. The seed value
is all 1s (see Table 14 for the initial values). The output is a
parallel representation of the serial PN9 sequence in MSB-first
format. The first output word is the first 14 bits of the PN9
sequence in MSB aligned form.
The PN sequence long pattern produces a pseudorandom bit
sequence that repeats itself every 223 1 or 8,388,607 bits. A
description of the PN sequence and how it is generated can be
found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The
seed value is all 1s (see Table 14 for the initial values) and the
AD9653 inverts the bit stream with relation to the ITU standard.
The output is a parallel representation of the serial PN23 sequence
in MSB-first format. The first output word is the first 14 bits of the
PN23 sequence in MSB aligned form
Table 14. PN Sequence
Sequence
Initial
Value
First Three Output Samples
(MSB First) Twos Complement
PN Sequence Short
0x1FE0
0x1DF1, 0x3CC8, 0x294E
PN Sequence Long
0x1FFF
0x1FE0, 0x2001, 0x1C00
Consult the Memory Map section for information on how to
change these additional digital output timing features through
the SPI.
SDIO/OLM Pin
For applications that do not require SPI mode operation, the
CSB pin is tied to AVDD, and the SDIO/OLM pin controls the
output lane mode according to Table 15.
Note that, when the CSB pin is tied to AVDD, the AD9653 DCS
is on by default and remains on unless the part is placed in SPI
mode and controlled via the SPI. Refer to the Clock Duty Cycle
section for more information on the DCS.
For applications where the SDIO/OLM pin is not used, CSB
should be tied to AVDD. When using the one-lane mode, the
conversion rate should be ≤62.5 MSPS to meet the maximum
output rate of 1 Gbps.
Table 15. Output Lane Mode Pin Settings
OLM Pin
Voltage
Output Mode
AVDD (Default)
Two-lane. 1× frame, 16-bit serial output
GND
One-lane. 1× frame, 16-bit serial output
SCLK/DTP Pin
The SCLK/DTP pin is used to select the digital test pattern
(DTP) for applications that do not require SPI mode operation.
This pin can enable a single digital test pattern if it and the CSB
pin are held high during device power-up. When SCLK/DTP is
tied to AVDD, the ADC channel outputs shift out the following
pattern: 1000 0000 0000 0000. The FCO and DCO function
normally while all channels shift out the repeatable test pattern.
This pattern allows the user to perform timing alignment
adjustments among the FCO, DCO, and output data. This pin has
an internal 10 k resistor to GND. It can be left unconnected.
Table 16. Digital Test Pattern Pin Settings
Selected DTP
DTP Voltage
Resulting
D0±x and D1±x
Normal Operation
10 kΩ to AGND
Normal operation
DTP
AVDD
1000 0000 0000 0000
Additional and custom test patterns can also be observed when
commanded from the SPI port. Consult the Memory Map
section for information about the options available.
CSB Pin
The CSB pin should be tied to AVDD for applications that do
not require SPI mode operation. By tying CSB high, all SCLK
and SDIO information is ignored.
Note that, when the CSB pin is tied to AVDD, the AD9653 DCS
is on by default and remains on unless the part is placed in SPI
mode and controlled via the SPI. Refer to the Clock Duty Cycle
section for more information on the DCS.
RBIAS Pin
To set the internal core bias current of the ADC, place a
10.0 k, 1% tolerance resistor to ground at the RBIAS pin.
OUTPUT TEST MODES
The output test options are described in Table 13 and controlled by
the output test mode bits at Address 0x0D. When an output test
mode is enabled, the analog section of the ADC is disconnected
from the digital back-end blocks and the test pattern is run
through the output formatting block. Some of the test patterns
are subject to output formatting, and some are not. The PN
generators from the PN sequence tests can be reset by setting
Bit 4 or Bit 5 of Register 0x0D. These tests can be performed
with or without an analog signal (if present, the analog signal is
ignored), but they do require an encode clock. For more
information, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
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