參數(shù)資料
型號(hào)： AD9639BCPZ-170
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 22/36頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12B 170MSPS QUAD 72LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 210M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 1.39W
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 72-LFCSP
包裝： 托盤
輸入數(shù)目和類型： 8 個(gè)單端，單極；4 個(gè)差分，單極
Data Sheet
AD9639
Rev. B | Page 29 of 36
SERIAL PORT INTERFACE (SPI)
The AD9639 serial port interface allows the user to configure the
converter for specific functions or operations through a structured
register space provided in the ADC. The SPI can provide the
user with additional flexibility and customization, depending
on the application. Addresses are accessed via the serial port
and can be written to or read from via the port. Memory is
organized into bytes that can be further divided into fields, as
documented in the Memory Map section. Detailed operational
information can be found in the Analog Devices, Inc., AN-877
Application Note, Interfacing to High Speed ADCs via SPI.
Four pins define the SPI: SCLK, SDI/SDIO, SDO, and CSB (see
Table 13). The SCLK pin is used to synchronize the read and
write data presented to the ADC. The SDI/SDIO pin is a dual-
purpose pin that allows data to be sent to and read from the
internal ADC memory map registers. The SDO pin is used in
4-wire mode to read back data from the part. The CSB pin is an
active low control that enables or disables the read and write cycles.
Table 13. Serial Port Pins
Pin
Function
SCLK
Serial clock. Serial shift clock input. SCLK is used to
synchronize serial interface reads and writes.
SDI/SDIO
Serial data input/output. Dual-purpose pin that
typically serves as an input or an output, depending
on the SPI wire mode, the instruction sent, and the
relative position in the timing frame.
SDO
Serial data output. Used only in 4-wire SPI mode.
When set, the SDO pin becomes active. When cleared,
the SDO pin remains in three-state and all read data
is routed to the SDI/SDIO pin.
CSB
Chip select bar (active low). This control gates the
read and write cycles.
The falling edge of CSB in conjunction with the rising edge of
SCLK determines the start of the framing sequence. During the
instruction phase, a 16-bit instruction is transmitted, followed
by one or more data bytes, which is determined by Bit Field W0
and Bit Field W1. An example of the serial timing and its defini-
tions can be found in Figure 63 and Table 14.
During normal operation, CSB is used to signal to the device
that SPI commands are to be received and processed. When
CSB is brought low, the device processes SCLK and SDI/SDIO
to execute instructions. Normally, CSB remains low until the
communication cycle is complete. However, if connected to a
slow device, CSB can be brought high between bytes, allowing
older microcontrollers enough time to transfer data into shift
registers. CSB can be stalled when transferring one, two, or three
bytes of data. When W0 and W1 are set to 11, the device enters
streaming mode and continues to process data, either reading
or writing, until CSB is taken high to end the communication
cycle. This allows complete memory transfers without requiring
additional instructions. Regardless of the mode, if CSB is taken
high in the middle of a byte transfer, the SPI state machine is
reset and the device waits for a new instruction.
In addition to the operation modes, the SPI port configuration
influences how the AD9639 operates. For applications that do
not require a control port, the CSB line can be tied high. This
places the SDI/SDIO pin into its secondary mode, as defined in
the SDI/SDIO Pin section. CSB can also be tied low to enable
2-wire mode. When CSB is tied low, SCLK and SDI/SDIO are
the only pins required for communication. Although the device
is synchronized during power-up, the user should ensure that
the serial port remains synchronized with the CSB line when
using this mode. When operating in 2-wire mode, it is recom-
mended that a 1-, 2-, or 3-byte transfer be used exclusively.
Without an active CSB line, streaming mode can be entered but
not exited.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used to both program the chip and read the
contents of the on-chip memory. If the instruction is a readback
operation, performing a readback causes the SDI/SDIO pin to
change from an input to an output at the appropriate point in
the serial frame.
Data can be sent in MSB first or LSB first mode. MSB first mode
is the default at power-up and can be changed by adjusting the
configuration register (Address 0x00). For more information
about this and other features, see the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
HARDWARE INTERFACE
The pins described in Table 13 constitute the physical interface
between the user’s programming device and the serial port of
the AD9639. The SCLK and CSB pins function as inputs when
using the SPI. The SDI/SDIO pin is bidirectional, functioning as
an input during write phases and as an output during readback.
If multiple SDI/SDIO pins share a common connection, ensure
that proper VOH levels are met. Assuming the same load for each
AD9639, Figure 62 shows the number of SDI/SDIO pins that
can be connected together and the resulting VOH level. This
interface is flexible enough to be controlled by either serial
PROMs or PIC microcontrollers, providing the user with an
alternative method, other than a full SPI controller, to program
the ADC (see the AN-812 Application Note).
For users who wish to operate the ADC without using the
SPI, remove any connections from the CSB, SCLK, SDO, and
SDI/SDIO pins. By disconnecting these pins from the control bus,
the ADC can function in its most basic operation. Each of these
pins has an internal termination that floats to its respective level.
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