參數(shù)資料
型號： AD9639BCPZ-170
廠商： Analog Devices Inc
文件頁數(shù)： 11/36頁
文件大?。?/td> 0K
描述： IC ADC 12B 170MSPS QUAD 72LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 210M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 1.39W
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 72-LFCSP
包裝： 托盤
輸入數(shù)目和類型： 8 個單端，單極；4 個差分，單極
Data Sheet
AD9639
Rev. B | Page 19 of 36
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9639 sample clock inputs
(CLK+ and CLK) should be clocked with a differential signal.
This signal is typically ac-coupled to the CLK+ and CLK pins
via a transformer or capacitors. These pins are biased internally
to 1.2 V and require no additional biasing.
Figure 43 shows a preferred method for clocking the AD9639. The
low jitter clock source is converted from a single-ended signal
to a differential signal using an RF transformer. The back-to-
back Schottky diodes across the secondary transformer limit
clock excursions into the AD9639 to approximately 0.8 V p-p
differential. This helps to prevent the large voltage swings of the
clock from feeding through to other portions of the AD9639,
and it preserves the fast rise and fall times of the signal, which
are critical to low jitter performance.
0.1F
SCHOTTKY
DIODES:
HSMS-2812
CLK+
50
CLK–
CLK+
ADT1-1WT, 1:1Z
XFMR
ADC
AD9639
07973-
018
Figure 43. Transformer-Coupled Differential Clock
Another option is to ac-couple a differential PECL signal to the
sample clock input pins as shown in Figure 44. The AD9510/
family of clock drivers offers excellent jitter performance.
100
0.1F
240
240
50
*
50
*
CLK
CLK–
CLK+
ADC
AD9639
PECL DRIVER
CLK+
CLK–
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515/
AD9516/AD9518
*50 RESISTORS ARE OPTIONAL.
07973-
019
Figure 44. Differential PECL Sample Clock
10
0
0.1F
50*
CLK
CLK–
CLK+
ADC
AD9639
LVDS DRIVER
CLK+
CLK–
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515/
AD9516/AD9518
*50 RESISTORS ARE OPTIONAL.
07973-
020
Figure 45. Differential LVDS Sample Clock
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be driven directly from a CMOS gate, and the
CLK pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 k resistor (see Figure 46). Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is
designed to withstand input voltages of up to 3.3 V and,
therefore, offers several selections for the drive logic voltage.
0.1F
39
k
50
*
0.1F
CLK
CLK–
CLK+
ADC
AD9639
CMOS DRIVER
CLK+
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515/
AD9516/AD9518
*50 RESISTOR IS OPTIONAL.
OPTIONAL
100
07973-
021
Figure 46. Single-Ended 1.8 V CMOS Sample Clock
0.1F
CLK
0.1F
CLK–
CLK+
ADC
AD9639
OPTIONAL
100
CMOS DRIVER
CLK+
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515/
AD9516/AD9518
*50 RESISTOR IS OPTIONAL.
50
*
07973-
022
Figure 47. Single-Ended 3.3 V CMOS Sample Clock
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to the clock duty cycle. Commonly, a 5% tolerance
is required on the clock duty cycle to maintain dynamic perfor-
mance characteristics.
The AD9639 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling edge, providing an internal clock signal with a
nominal 50% duty cycle. This allows a wide range of clock input
duty cycles without affecting the performance of the AD9639.
When the DCS is on (default), noise and distortion performance
are nearly flat for a wide range of duty cycles. However, some
applications may require the DCS function to be off. If so, keep
in mind that the dynamic range performance may be affected
when operated in this mode. See the Memory Map section for
more details on using this feature.
Jitter in the rising edge of the input is an important concern,
and it is not reduced by the internal stabilization circuit. The
duty cycle control loop does not function for clock rates of less
than 50 MHz nominal. It is not recommended that this ADC
clock be dynamic in nature. Moving the clock around dynami-
cally requires long wait times for the back end serial capture to
retime and resynchronize to the receiving logic. This long time
constant far exceeds the time that it takes for the DCS and the
PLL to lock and stabilize. Only in rare applications would it be
necessary to disable the DCS circuitry in the clock register (see
Address 0x09 in Table 15). Keeping the DCS circuit enabled is
recommended to maximize ac performance.
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