參數(shù)資料
型號： AD9633BCPZRL7-105
廠商： Analog Devices Inc
文件頁數(shù)： 28/40頁
文件大?。?/td> 0K
描述： IC ADC 12BIT SRL 105MSPS 48LFCSP
標準包裝： 750
位數(shù)： 12
采樣率（每秒）： 105M
數(shù)據(jù)接口： LVDS，串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 473mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-WFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-WQ（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個差分，雙極
AD9633
Data Sheet
Rev. 0 | Page 34 of 40
MEMORY MAP REGISTER TABLE
The AD9633 uses a 3-wire interface and 16-bit addressing and,
therefore, Bit 0 and Bit 7 in Register 0x00 are set to 0, and Bit 3
and Bit 4 are set to 1. When Bit 5 in Register 0x00 is set high,
the SPI enters a soft reset, where all of the user registers revert
to their default values and Bit 2 is automatically cleared.
Table 17.
Addr
(Hex)
Parameter
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Comments
Chip Configuration Registers
0x00
SPI port
configuration
0 =
SDO
active
LSB first
Soft reset
1 =
16-bit
address
1 =
16-bit
address
Soft
reset
LSB first
0 = SDO
active
0x18
The nibbles
are mirrored
so that LSB-
first or MSB-
first mode
registers
correctly.
The default
for ADCs is
16-bit mode.
0x01
Chip ID (global)
8-bit chip ID, Bits[7:0]
AD9633 0x90 = quad 12-bit 80 MSPS/105 MSPS/125 MSPS serial LVDS
0x90
Unique
chip ID
used to differ-
entiate
devices; read
only.
0x02
Chip grade
(global)
Open
Speed grade ID[6:4]
100 = 80 MSPS
101 = 105 MSPS
110 = 125 MSPS
Open
Unique speed
grade ID used
to differentiate
graded devices;
read only.
Device Index and Transfer Registers
0x05
Device index
Open
Clock
Channel
DCO
Clock
Channel
FCO
Data
Channel
D
Data
Channel
C
Data
Channel
B
Data
Channel
A
0x3F
Bits are set
to determine
which device
on chip receives
the next write
command. The
default is all
devices on chip.
0xFF
Transfer
Open
Initiate
override
0x00
Set resolution/
sample rate
override.
Global ADC Function Registers
0x08
Power modes
(global)
Open
External
power-
down pin
function
0 = full
power-
down
1 =
standby
Open
Power mode
00 = chip run
01 = full power-down
10 = standby
11 = reset
0x00
Determines
various generic
modes of chip
operation.
0x09
Clock (global)
Open
Duty
cycle
stabilize
0 = off
1 = on
0x01
Turns duty cycle
stabilizer on or
off.
0x0B
Clock divide
(global)
Open
Clock divide ratio[2:0]
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
0x00
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