參數(shù)資料
型號: AD9627-125EBZ
廠商: Analog Devices Inc
文件頁數(shù): 8/76頁
文件大?。?/td> 0K
描述: IC A/D 12BIT 125MSPS DL EVAL BRD
標準包裝: 1
ADC 的數(shù)量: 2
位數(shù): 12
采樣率(每秒): 125M
數(shù)據(jù)接口: 串行
輸入范圍: 2 Vpp
在以下條件下的電源(標準): 900mW @ 125MSPS
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD9627
已供物品: 板,電源
AD9627
Rev. B | Page 16 of 76
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
06
57
1-
0
06
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
D3A
D4A
D5A
DR
G
N
D
DR
V
DD
D6A
D7A
DV
D
D8A
D9A
D10A
D11A
(
M
S
B
)
FD
0
A
FD
1
A
FD
2
A
FD
3
A
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
DRG
ND
D3B
D2B
D1B
D0B
(
L
S
B
)
DNC
DV
DD
FD
3
B
FD
2
B
FD
1
B
FD
0
B
SYN
C
CS
B
CL
K
CL
K
+
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DRVDD
D4B
D5B
D6B
D7B
D8B
D9B
D10B
D11B (MSB)
DCOB
DCOA
DNC
D0A (LSB)
D1A
D2A
SCLK/DFS
SDIO/DCS
AVDD
VIN+B
VIN–B
RBIAS
CML
SENSE
VREF
VIN–A
VIN+A
AVDD
SMI SDFS
SMI SCLK/PDWN
SMI SDO/OEB
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PIN 1
INDICATOR
AD9627
PARALLEL CMOS
TOP VIEW
(Not to Scale)
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
NOTES
1. DNC = DO NOT CONNECT.
2. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND.
Figure 6. LFCSP Parallel CMOS Pin Configuration (Top View)
Table 11. Pin Function Descriptions (Parallel CMOS Mode)
Pin No.
Mnemonic
Type
Description
ADC Power Supplies
20, 64
DRGND
Ground
Digital Output Ground.
1, 21
DRVDD
Supply
Digital Output Driver Supply (1.8 V to 3.3 V).
24, 57
DVDD
Supply
Digital Power Supply (1.8 V Nominal).
36, 45, 46
AVDD
Supply
Analog Power Supply (1.8 V Nominal).
0
AGND
Ground
Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package.
12, 13, 58, 59
DNC
Do Not Connect.
ADC Analog
37
VIN+A
Input
Differential Analog Input Pin (+) for Channel A.
38
VINA
Input
Differential Analog Input Pin () for Channel A.
44
VIN+B
Input
Differential Analog Input Pin (+) for Channel B.
43
VINB
Input
Differential Analog Input Pin () for Channel B.
39
VREF
Input/Output
Voltage Reference Input/Output.
40
SENSE
Input
Voltage Reference Mode Select. See Table 14 for details.
42
RBIAS
Input/Output
External Reference Bias Resistor.
41
CML
Output
Common-Mode Level Bias Output for Analog Inputs.
49
CLK+
Input
ADC Clock Input—True.
50
CLK
Input
ADC Clock Input—Complement.
ADC Fast Detect Outputs
29
FD0A
Output
Channel A Fast Detect Indicator. See Table 17 for details.
30
FD1A
Output
Channel A Fast Detect Indicator. See Table 17 for details.
31
FD2A
Output
Channel A Fast Detect Indicator. See Table 17 for details.
32
FD3A
Output
Channel A Fast Detect Indicator. See Table 17 for details.
53
FD0B
Output
Channel B Fast Detect Indicator. See Table 17 for details.
54
FD1B
Output
Channel B Fast Detect Indicator. See Table 17 for details.
55
FD2B
Output
Channel B Fast Detect Indicator. See Table 17 for details.
56
FD3B
Output
Channel B Fast Detect Indicator. See Table 17 for details.
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