參數(shù)資料
型號: AD9627-125EBZ
廠商: Analog Devices Inc
文件頁數(shù): 37/76頁
文件大?。?/td> 0K
描述: IC A/D 12BIT 125MSPS DL EVAL BRD
標準包裝: 1
ADC 的數(shù)量: 2
位數(shù): 12
采樣率(每秒): 125M
數(shù)據(jù)接口: 串行
輸入范圍: 2 Vpp
在以下條件下的電源(標準): 900mW @ 125MSPS
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD9627
已供物品: 板,電源
AD9627
Rev. B | Page 42 of 76
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SDIO/DCS pin, the SCLK/DFS pin, the SMI SDO/OEB pin,
and the SMI SCLK/PDWN pin serve as standalone CMOS-
compatible control pins. When the device is powered up, it is
assumed that the user intends to use the pins as static control
lines for the duty cycle stabilizer, output data format, output
enable, and power-down feature control. In this mode, the CSB
chip select should be connected to AVDD, which disables the
serial port interface.
Table 23. Mode Selection
Pin
External
Voltage
Configuration
SDIO/DCS
AVDD (default)
Duty cycle stabilizer enabled
AGND
Duty cycle stabilizer disabled
SCLK/DFS
AVDD
Twos complement enabled
AGND (default)
Offset binary enabled
SMI SDO/OEB
AVDD
Outputs in high impedance
AGND (default)
Outputs enabled
SMI SCLK/PDWN
AVDD
Chip in power-down or
standby
AGND (default)
Normal operation
SPI ACCESSIBLE FEATURES
Table 24 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in Application Note AN-877, Interfacing to High Speed ADCs via
SPI. The AD9627 part-specific features are described in detail
following Table 25, the external memory map register table.
Table 24. Features Accessible Using the SPI
Feature Name
Description
Mode
Allows the user to set either power-down mode
or standby mode
Clock
Allows the user to access the DCS via the SPI
Offset
Allows the user to digitally adjust the
converter offset
Test I/O
Allows the user to set test modes to have
known data on output bits
Output Mode
Allows the user to set up outputs
Output Phase
Allows the user to set the output clock polarity
Output Delay
Allows the user to vary the DCO delay
VREF
Allows the user to set the reference voltage
DON’T CARE
SDIO
SCLK
CSB
tS
tDH
tCLK
tDS
tH
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
tLOW
tHIGH
0
657
1-
07
3
Figure 73. Serial Port Interface Timing Diagram
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