參數(shù)資料
型號(hào): AD9577BCPZ-RL
廠商: Analog Devices Inc
文件頁數(shù): 38/44頁
文件大?。?/td> 0K
描述: IC CLK GEN PLL DUAL 40LFCSP
標(biāo)準(zhǔn)包裝: 2,500
系列: PCI Express® (PCIe)
類型: 扇出緩沖器(分配),網(wǎng)絡(luò)時(shí)鐘發(fā)生器,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),PCI Express(PCIe),SONET/SDH
輸入: 時(shí)鐘,晶體
輸出: LVCMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:5
差分 - 輸入:輸出: 無/是
頻率 - 最大: 637.5MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 40-WFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 40-LFCSP-WQ(6x6)
包裝: 帶卷 (TR)
Data Sheet
AD9577
Rev. 0 | Page 43 of 44
1
10
VSCA
VSI2C
REFOUT
VSREFOUT
VSX
REFCLK
XT2
XT1
REFSEL
VSCB
30
21
OUT3P
VSFB
VSM
SSCG
VSFA
OUT1N
OUT1P
VSOB1A
OUT3N
VSOB3B
11
20
T
S
T
1B
T
S
T
2B
L
D
O
G
N
D
O
U
T
2N
G
N
D
O
U
T
2P
V
S
O
B
2B
M
A
R
G
IN
V
S
V
B
O
U
T
0N
O
U
T
0P
G
N
D
G
N
D
S
C
L
V
S
V
A
T
S
T
2A
40
M
A
X
_B
W
V
S
O
B
0A
31
S
D
A
AD9577
22pF
CD
VS
CD
220nF
CD
VS
DO NOT CONNECT OTHER TRACES
TO PIN 15, PIN 16, PIN 35, AND PIN 36.
CAPACITORS CD CONSIST OF
100nF IN PARALLEL WITH 10nF.
10k
VS
10k
VS
50
50
50
50
50
VS
127
83
127
83
VS
127
83
127
83
VS
127
83
127
83
50
VS
127
83
127
83
092
84
-055
CD
Figure 50. Typical LVPECL Application Circuit
POWER AND GROUNDING CONSIDERATIONS AND POWER SUPPLY REJECTION
Many applications seek high speed and performance under less
than ideal operating conditions. In these application circuits,
the implementation and construction of the PCB is as important
as the circuit design. Proper RF techniques must be used for
device selection, placement, and routing, as well as for power
supply bypassing and grounding to ensure optimum performance.
Each power supply pin should have independent decoupling and
connections to the power supply plane. It is recommended that the
device exposed paddle be directly connected to the ground plane
by a grid of at least nine vias. Care should be taken to ensure that
the output traces cannot couple onto the reference or crystal input
circuitry.
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